OpenCores
no use no use 1/1 no use no use
Simulator ORC
by Unknown on Feb 2, 2004
Not available!
When I try to build or1ksim and try to run it, I have also encountered the problems that are mentioned in christian mail. Any body wants to help to E-mail one page write up on using or1ksim. I will try those instructions and I can enhance it with my experience. Thanks in advance for your help. --babu ----- Original Message ----- From: John.Smith@y... To: openrisc@o... Date: Wed, 29 Oct 2003 04:21:59 +0100 Subject: Re: [openrisc] Simulator ORC
I think or1ksim is hard to use also.It will be better when there is a tutorial about or1ksim.^_^ ----- Original Message ----- From: christian@m... To: openrisc@o... Date: Sat, 25 Oct 2003 19:19:32 +0200 Subject: [openrisc] Simulator ORC
>
>
> Hello,
>
> I have installed the architectural simulator. I follow the

README
> instructions in order to install uClinux on simulator. It

seems
> working
> because I can output data message into uart0.tx (command less
> uart0.tx) file : or32-uclinux-sim -f sim.cfg linux. But i

don't
> see
> anything in the second file uart0.rx. What can I do to

correct it?
>
> Is it correct that i cannot run the testbench simulator?
>
> By typing 'make all check' (or1ksim/testbench), many errors

occur.
>
> Also, I would like to get some example in order to use the
> simulator.
> Like run some programs on this simulator.
>
> Thanks
>
> Christian
>



Simulator ORC
by Unknown on Feb 2, 2004
Not available!
* bkandimalla@yahoo.com (bkandimalla@yahoo.com) wrote:
When I try to build or1ksim and try to run it, I have also encountered
the problems that are mentioned in christian mail.

Any body wants to help to E-mail one page write up on using or1ksim. I
will try those instructions and I can enhance it with my experience.
ok, i'll start by writing some basic stuff and you can enhance. when you do that please submit resulting document, so we can put it into cvs for other to use. first you start the simulator: or32-uclinux-sim -f sim.cfg vmlinux -i where: or32-uclinux-sim : simulator binary, can be named diffrently -f sim.cfg : tells simulator configuration you wanna use vmlinux : binary (in elf or coff format) to simulate -i : interactive (don't automaticaly start executing) : let's just take linux as an example... you'd see something similar to: Reading script file from 'sim.cfg'... Verbose on, simdebug off, interactive prompt on Machine initialization... Clock cycle: 4ns No data cache. No instruction cache. BPB simulation off. BTIC simulation off. Building automata... done, num uncovered: 0/212. Parsing operands data... done. loadcode: filename vmlinux startaddr=0 virtphy_transl=0 Not COFF file format ELF type: 0x0002 ELF machine: 0x8472 ELF version: 0x00000001 ELF sec = 30 Section: .text, vaddr: 0xc0000000, paddr: 0xf0000000, offset: 0x00001000, size: 0x0017f820 Section: .rodata, vaddr: 0xc0180000, paddr: 0xf0180000, offset: 0x00181000, size: 0x00017bbd Section: .kstrtab, vaddr: 0xc0197bbd, paddr: 0xf0197bbd, offset: 0x00198bbd, size: 0x000035f4 Section: .data, vaddr: 0xc019c000, paddr: 0xf019c000, offset: 0x0019d000, size: 0x00016da4 Section: ___ex_table, vaddr: 0xc01b2da4, paddr: 0xf01b2da4, offset: 0x001b3da4, size: 0x000009c8 Section: ___ksymtab, vaddr: 0xc01b376c, paddr: 0xf01b376c, offset: 0x001b476c, size: 0x00001c68 Section: .initcall.init, vaddr: 0xc01b6000, paddr: 0xf01b6000, offset: 0x001b7000, size: 0x0000009c Section: .initrd, vaddr: 0xc01b8000, paddr: 0xf01b8000, offset: 0x001b8000, size: 0x00100000 WARNING: dependstats stats must be enabled to do history analisis. Resetting 1 UART(s). UART0 at 0x90000000 uses 0 WARNING: Keyboard has problems with RX file stream. Resetting Tick Timer. Resetting Power Management. Resetting PIC. Resetting memory controller. Starting at 0x00000000 : this just tells you where sections in binary were loaded : and some diagnostics Exception 0x100 (Reset) at 0x0, EA: 0x0, ppc: 0x0, npc: 0x4, #0 : the or1k architecture states that 0x100 is reset vector : so this is simulator starts execution. till now all it has done : is place (hopefuly) executable code into memory (using binary LMA) (sim) : you get this prompt. maybe we can try with help (sim) help q - quit simulator r - display all registers t - execute next instruction run [] - execute instructions, no reg dump if hush pr - patch register with dm [] - display memory from to de [] - debug insn memory pm - patch memory location with pc - patch PC register with break - toggle breakpoint at address breaks - print all set breakpoints reset - simulator reset hist - execution history stall - stalls the processor and gives control to the debugger stats - execution statistics num or clear it. info - configuration info (caches etc.) dv [] [] - dumps memory as verilog (use redirect) dh [] - dumps memory as hex code (use redirect) > - redirect simulator stdout to (and not emulated PRINTF) set = - set configuration. See sim.cfg for more information. debug - toggles simulator debug mode mprofiler [-f filename] [-g group] from to -d --detail detailed output -p --pretty pretty output -a --access output accesses only -w --width output by width -f --filename filename specify mprofile file [sim.mprofile] -g --group bits group 2^bits successive addresses together [2] -h --help output this screen profiler [-c] [-q] -g [profile_file_name] -c --cumulative cumulative sum of cycles in functions -q --quiet suppress messages -g --generate [profile_file_name] output profiling results to stdout/profile_file_name cuc - enters Custom Unit Compiler command prompt help - available commands (this list) : ok nice. useful for us will be 't' - one insn forward, : 'r' show registers, 'break' set breakpooints, and 'run' : lets just try 't' (sim) t 00000100: : a8600001 l.ori r3,r0,0x1 (executed) [time 4ns, #1] : first line gives you info about just executed insn 00000104: : c0001811 l.mtspr r0,r3,0x11 (next insn) : this is next instruction GPR00: 00000000 GPR01: 00000000 GPR02: 00000000 GPR03: 00000001 GPR04: 00000000 GPR05: 00000000 GPR06: 00000000 GPR07: 00000000 GPR08: 00000000 GPR09: 00000000 GPR10: 00000000 GPR11: 00000000 GPR12: 00000000 GPR13: 00000000 GPR14: 00000000 GPR15: 00000000 GPR16: 00000000 GPR17: 00000000 GPR18: 00000000 GPR19: 00000000 GPR20: 00000000 GPR21: 00000000 GPR22: 00000000 GPR23: 00000000 GPR24: 00000000 GPR25: 00000000 GPR26: 00000000 GPR27: 00000000 GPR28: 00000000 GPR29: 00000000 GPR30: 00000000 GPR31: 00000000 flag: 0 : and this is state of the registers : let's try again (sim) t 00000104: : c0001811 l.mtspr r0,r3,0x11 (executed) [time 8ns, #2] 00000108: : 1860f000 l.movhi r3,0xf000 (next insn) GPR00: 00000000 GPR01: 00000000 GPR02: 00000000 GPR03: 00000001 GPR04: 00000000 GPR05: 00000000 GPR06: 00000000 GPR07: 00000000 GPR08: 00000000 GPR09: 00000000 GPR10: 00000000 GPR11: 00000000 GPR12: 00000000 GPR13: 00000000 GPR14: 00000000 GPR15: 00000000 GPR16: 00000000 GPR17: 00000000 GPR18: 00000000 GPR19: 00000000 GPR20: 00000000 GPR21: 00000000 GPR22: 00000000 GPR23: 00000000 GPR24: 00000000 GPR25: 00000000 GPR26: 00000000 GPR27: 00000000 GPR28: 00000000 GPR29: 00000000 GPR30: 00000000 GPR31: 00000000 flag: 0 : we can also set a breakpoint (sim) break 0x900 Breakpoint at 0x00000900 set. : now run it forever (-1) without register output (sim) run -1 hush ' ' 'C' 'o' 'p' 'y' 'i' 'n' 'g' ' ' 'L' 'i' 'n' 'u' 'x' '.' '.' '.' ' ' 'O' 'k' ',' ' ' 'b' 'o' 'o' 't' 'i' 'n' 'g' ' ' 't' 'h' 'e' ' ' 'k' 'e' 'r' 'n' 'e' 'l' '.' ' ' ' : this is output out of UART. it's also stored in uart0.tx : tx as transmit. you can input data (into simulator) over UART : by writing into uart0.rx (all this is configurable in sim.cfg) Exception 0xa00 (Insn TLB Miss) at 0x2224, EA: 0x2228, ppc: 0x2228, npc: 0x222c, #6626054 : this is info about exception that happened Exception 0xa00 (Insn TLB Miss) at 0x22a8, EA: 0xc0002c9c, ppc: 0xc0002c9c, npc: 0xc0002ca0, #6626130 Exception 0x900 (Data TLB Miss) at 0xc0002ca0, EA: 0xc01a7ff4, ppc: 0xc0002ca0, npc: 0xc0002ca4, #6626177 Breakpoint hit. : ok we hit the breakpoint, lets see what's in the ESR register (sim) info VR : 0x12000000 UPR : 0x0000e83f SR : 0x00008601 MACLO: 0x00000000 MACHI: 0x00000000 EPCR0: 0xc0002ca0 EPCR1: 0x00000000 EEAR0: 0xc01a7ff4 EEAR1: 0x00000000 ESR0 : 0x00008661 ESR1 : 0x00000000 TTMR : 0x00000000 TTCR : 0x008b8a68 PICMR: 0x00000000 PICSR: 0x00000000 PPC: 0xc0002ca0 NPC : 0x00000900 : : [cut] there is lots of other info printed : let's finish for now 'q' (quit) (sim) q : simple enough ;) ?
> I have installed the architectural simulator. I follow the

> README
> instructions in order to install uClinux on simulator. It

> seems
> working
> because I can output data message into uart0.tx (command less
> uart0.tx) file : or32-uclinux-sim -f sim.cfg linux. But i

> don't
> see
> anything in the second file uart0.rx. What can I do to

> correct it?


you write into *.rx file to send data over (simulated) UART into
simulator. after the uclinux is booted try:

echo "ls -la" >> uart0.rx

and wait a bit. see ?

> Is it correct that i cannot run the testbench simulator?
>
> By typing 'make all check' (or1ksim/testbench), many errors

> occur.

right. i've see that testbenches are boroken. it's not 'correct' but
unfortunatly that's the current situation. we'll fix it soon ;)

> Also, I would like to get some example in order to use the
> simulator.
> Like run some programs on this simulator.


done that.

best regards,
p.

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