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Xess Synplify project has error
by Unknown on Feb 5, 2004 |
Not available! | ||
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@E: or1200_cpu.v(415): port genpc_stop_prefetch does not exist
@E:"d:\or1k\xess\xsv_fpga\orp_soc\rtl\verilog\or1200 \or1200_cpu.v":415:2:415:21 1 Verilog Compiler error |
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