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debug interface problem
by Unknown on Feb 5, 2004 |
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HI: I'm developing a pc software to debug or1200 via jtag port. I have read the "DbgSupp.pdf", and can access wishbone and spr successfully. But i can't find how to access memory in data cache and instruction cache. Can i access the momery in cache by access spr? regards, Kevin |
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debug interface problem
by Unknown on Feb 5, 2004 |
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Hi!
Currently you cannot access any of the mentioned RAMs. Are you aware of gdb -- debugger we use? Maybe it would be great to add support for it, so that one could run application instead of MBIST and save some gates and maybe also testing time? best regards, Marko HI: I'm developing a pc software to debug or1200 via jtag port. I have read the "DbgSupp.pdf", and can access wishbone and spr successfully. But i can't find how to access memory in data cache and instruction cache. Can i access the momery in cache by access spr? |
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