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label in generated asm code
by Unknown on Feb 10, 2004
Not available!
label in generated asm code
by Unknown on Feb 10, 2004
Not available!
Hi all,
I have a question about the following code.

l.slli r3,r11,2
l.movhi r4,hi(.L145) # move immediate (high)
l.ori r4,r4,lo(.L145) # move immediate (low)
l.add r3,r3,r4
l.lwz r4,0(r3) # SI load
l.jr r4
l.nop # nop delay slot
.section .rodata
.align 4
.align 4
.L145:
.word .L108
.word .L113
.word .L144
.word .L114
.word .L119
.word .L120
.word .L144
.word .L121
.word .L144
.word .L144
.word .L122
.word .L144
.word .L144
.word .L127
.word .L144
.word .L134
.word .L135
.word .L144
.word .L136
.word .L137
.word .L138
.word .L144
.word .L139
.text
.L108:
l.addi r4,r0,1 # move immediate
l.movhi r3,hi(_Main_Bitstream_Flag) # move immediate (high)
l.ori r3,r3,lo(_Main_Bitstream_Flag) # move
immediate (low)
l.sw 0(r3),r4

From the above code, the pc goes to label .L145 with l.jr4. But I donot

know what the following asm code will do. Does it will run the code, in
label .L108, then label .L113....? Can you one give me some explaination?
Thank you very much.

Best Regards,

Stephen

label in generated asm code
by Unknown on Feb 10, 2004
Not available!
Firstly, I would strongly suggest you spend some time reading the architecture manual to understand how the OR32 instruction set works. You can find this here: http://www.opencores.org/cvsweb.shtml/or1k/docs/openrisc_arch3.doc Further comments inline.
l.slli r3,r11,2


Shift r11 left by two and put result in r3. This is creating a 32 bit offset
(i.e. 0,4,8 bytes) from an ordinal index (i.e. 0,1,2 etc.).

l.movhi r4,hi(.L145) # move immediate (high)
l.ori r4,r4,lo(.L145) # move immediate (low)


Load address of .L145 into r4

l.add r3,r3,r4


Add offset created above to it and store result in r3

l.lwz r4,0(r3) # SI load


Load data at address pointed to by r3 into r4.

l.jr r4
l.nop # nop delay slot


...and jump to it

.section .rodata
.align 4
.align 4
.L145:
.word .L108
.word .L113
.word .L144

[snip]
.word .L139
.text


The above is simply the jump table (I've shortened it a bit).

.L108:
l.addi r4,r0,1 # move immediate
l.movhi r3,hi(_Main_Bitstream_Flag) # move
immediate (high)
l.ori r3,r3,lo(_Main_Bitstream_Flag) # move
immediate (low)
l.sw 0(r3),r4


and this is the first bit of code it will execute via the jump table at
index 0.

I have annotated the code to show you in more detail:

l.slli r3,r11,2 # Let's says r11 = 2: r3 now contains 2

2, i.e. 8
l.movhi r4,hi(.L145) #
l.ori r4,r4,lo(.L145) # r4 now contains the address .L145
l.add r3,r3,r4 # r3 now contains r4 + 8 = .L145 + 8
l.lwz r4,0(r3) # r4 contains the data at .L145 + 8, which is

.L144 from the table below
l.jr r4 # So jump to .L144
l.nop # nop delay slot
.section .rodata
.align 4
.align 4
.L145:
.word .L108
.word .L113

#### .L145 + 8 is here
.word .L144


>From the above code, the pc goes to label .L145 with l.jr4.


No - see my explanation.

But I donot
know what the following asm code will do. Does it will run the code, in
label .L108, then label .L113....? Can you one give me some explaination?
You don't show enough of the code to know this - what happens at the end of the code after .L108? I would assume there is another jump here. Robert Cragie, Design Engineer _______________________________________________________________ Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK http://www.jennic.com Tel: +44 (0) 114 281 2655 _______________________________________________________________
label in generated asm code
by Unknown on Feb 10, 2004
Not available!
Hi Robert, Thank you for your explaination. In my source code, the jump table is coded in the function(generated by complier). i.e. .proc _function _function: ..... .... jump table .... .... .endproc _function If I move the jump the table to the end of function manually. i.e. .proc _function _function: ..... .... .... .... .endproc _function jump table The result of the function will be changed ? Thank you very much. Best Regards, Stephen Robert Cragie rcc@jennic.com> wrote: Firstly, I would strongly suggest you spend some time reading the architecture manual to understand how the OR32 instruction set works. You can find this here: http://www.opencores.org/cvsweb.shtml/or1k/docs/openrisc_arch3.doc Further comments inline.
l.slli r3,r11,2


Shift r11 left by two and put result in r3. This is creating a 32 bit offset
(i.e. 0,4,8 bytes) from an ordinal index (i.e. 0,1,2 etc.).

l.movhi r4,hi(.L145) # move immediate (high)
l.ori r4,r4,lo(.L145) # move immediate (low)


Load address of .L145 into r4

l.add r3,r3,r4


Add offset created above to it and store result in r3

l.lwz r4,0(r3) # SI load


Load data at address pointed to by r3 into r4.

l.jr r4
l.nop # nop delay slot


...and jump to it

.section .rodata
.align 4
.align 4
.L145:
.word .L108
.word .L113
.word .L144

[snip]
.word .L139
.text


The above is simply the jump table (I've shortened it a bit).

.L108:
l.addi r4,r0,1 # move immediate
l.movhi r3,hi(_Main_Bitstream_Flag) # move
immediate (high)
l.ori r3,r3,lo(_Main_Bitstream_Flag) # move
immediate (low)
l.sw 0(r3),r4


and this is the first bit of code it will execute via the jump table at
index 0.

I have annotated the code to show you in more detail:

l.slli r3,r11,2 # Let's says r11 = 2: r3 now contains 2

2, i.e. 8
l.movhi r4,hi(.L145) #
l.ori r4,r4,lo(.L145) # r4 now contains the address .L145
l.add r3,r3,r4 # r3 now contains r4 + 8 = .L145 + 8
l.lwz r4,0(r3) # r4 contains the data at .L145 + 8, which is

.L144 from the table below
l.jr r4 # So jump to .L144
l.nop # nop delay slot
.section .rodata
.align 4
.align 4
.L145:
.word .L108
.word .L113

#### .L145 + 8 is here
.word .L144


>From the above code, the pc goes to label .L145 with l.jr4.


No - see my explanation.

But I donot
know what the following asm code will do. Does it will run the code, in
label .L108, then label .L113....? Can you one give me some explaination?
You don't show enough of the code to know this - what happens at the end of the code after .L108? I would assume there is another jump here. Robert Cragie, Design Engineer _______________________________________________________________ Jennic Ltd, Furnival Street, Sheffield, S1 4QT, UK http://www.jennic.com Tel: +44 (0) 114 281 2655 _______________________________________________________________ _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc ¥²±þ§Þ¡B¶¼ºq¡B¤p¬P¬P... ®öº©¹aÁn ±¡¤ß³sô http://ringtone.yahoo.com.hk/ -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/openrisc/attachments/20040210/1691632b/attachment.htm
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