Hey !

I have added support for HW Breakpoints based on branch_qmem and tagged it
with rel_26. This rel_26 compared to the previous rel_24 (ignore rel_25) is
only different in added support for HW breakpoints and this support doesn't
affect the rest of the processor unless OR1200_DU_HWBKPTS is defined.

I'm planning to change the spec for HW Breakpoints a little bit because
currently changed watchpoints are too long (10 chained watchpoints is
becoming a critical path so I will break this into two separate chains).

Also an explanation on terminology (from discussion with Heiko). Watchpoint
is an internal event when conditions match. Watchpoint is chained from local
condition match and from previous watchpoints. Watchpoints can cause either
breakpoint or trap exception. Breakpoint can also be caused by other
exceptions. So what is this breakpoint - breakpoint is when the processor
gets stopped at certain point - breakpoint doesn't necessarily mean there is
an exception. So HW breakpoint support what it does it does cause trap
exception - but this in fact should only happen if there is DMR1[ETE]
enabled. Yes this DMR1[ETE] is different from DMR2[WGB]. With DMR2[WGB] one
can enable that certain watchpoints cause a breakpoint. Breakpoint like
explained above can simply be stalling the processor and giving control to
the development interface that can look at the registers, modify registers
etc (exactly what Jim Dempsey said), or breakpoint can also cause a trap
exception if enabled by DMR1[ETE] for resident debugger to do debugging (and
not external debugger / development interface). But the source for
breakpoint can also be an exception, in this case you would be using DSR/DRR
registers... I hope this explains a little better idea behind DMR1[ETE]. OK
I admit is does sound a little confusing so I will go and make some clean up
in terminology.

Should watchpoint counters DWCRx[COUNT] reset to zero whenever they match
DWCRx[MATCH]? I think yes. Alternative is that they keep counting but I
think it is better to reset (I also have a simple implementation of these
counters in mind as currently I know that when a counter would match its
condition to cause watchpoint, this would get stuck causing watchpoint all
the time... So I suggest it should reset.) Heiko how did you implement all
this stuff in or1ksim. I guess you had to assume a lot of stuff. We need to
put some of these details to the arch manual.

regards,
Damjan


enable define OR1200_DU_HWBKPTS.