Hi All, My name is Giles Hall and I work for Verisity Design, we develop advanced verification tools primarily targeted at hardware Verification. I am building a demo illustrating how to use our tools for CPU verification, and I decided to build this around the or1200 core. So far I have found several issues, I just want to know what is the right forum for reporting these issues. I am very happy to report what I find so you can improve the quality of the core implementation. Thanks Giles -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/openrisc/attachments/20040212/7f0e54ef/attachment.htm

Hi Damjan, Yes it is referring to just the RTL and I am working against the or1000 architecture spec. So here is what I found so far if these are old or not issues for some other reason please let me know and I make the appropriate adjustments to the test environment. I'm using the spec operisc_arc3.pdf Jan 2003. 1. l.xori : The xori instruction seems to sign extend the 'I' immediate value rather than zero extending it as specified on page 118 of the spec. 2. l.sub does not affect the carry flag 3. shift operators i.e l.sll, l.slr only use 5 bits rather than the specified 6 of the reg value or L as appropriate. I have a few more that I have not to the bottom of yet. I'm only spending a very small amount of time on this so not sure how quickly I can respond. Hope this is useful Giles -----Original Message----- From: openrisc-bounces@opencores.org [mailto:openrisc-bounces@opencores.org] On Behalf Of Damjan Lampret Sent: 12 February 2004 23:10 To: List about OpenRISC project Subject: Re: [openrisc] Verification help Hi Giles, excellent. You can either report to this list or to me - in any situation I will implement the changes in OR1200 RTL (assuming your reports address the issues in OR1200 RTL) regards, Damjan ----- Original Message ----- From: "Giles Hall" gileshall@btopenworld.com> To: "Opencores Mailing List" openrisc@opencores.org> Sent: Thursday, February 12, 2004 10:37 PM Subject: [openrisc] Verification help
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Hi Giles, excellent. You can either report to this list or to me - in any situation I will implement the changes in OR1200 RTL (assuming your reports address the issues in OR1200 RTL) regards, Damjan ----- Original Message ----- From: "Giles Hall" gileshall@btopenworld.com> To: "Opencores Mailing List" openrisc@opencores.org> Sent: Thursday, February 12, 2004 10:37 PM Subject: [openrisc] Verification help
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I can't remember why we changed it to sign extend, but gcc and or1ksim also
sign extend it. So arch manual is not in sync. I think it has to do with the
thinking that many times when you want to use l.xori is when you want to
invert a 32-bit variable and you would do something like l.xori rD,rA,-1. -1
would get sign extended into 32-bit ones and invert rA into rD. Something
along these lines...

What I will do is to change th arch manual as everything else (OR1200 RTL,
gcc, or1ksim) is in sync.



Correct.

The reason for this was that carry flag was added later and it was in fact
optional.



Correct.

On 32-bit implementations the 6th bit is ignored. The 64-bit implementations
will have to use a different compiler anyway. Anyhow 64-bit code will never
run on 32-bit implementations. The 6th bit was ignored to make the RTL a
little faster. I'm open to suggestions here to handle it properly in the
architecture - maybe to make a note.

Anyway very good observations !

regards,
Damjan