hey!

would anyone perhaps know of a simple way
to align certian instructions. for example i'd want compiler
generate all jump/branch instructions aligned to 8 bytes. (not jump targets)

best regards,
p.

??? Usually alignments are desired on the jump target (the destination of the jump) and not the address of the jump/branch instruction itself. ... I can see a possible reason for making an alignment such as if you have some sort of memory manager and if the processor core cannot handle a page fault in the middle of a jump/branch instruction. Or you also might want this alignment for cache reasons where a cache miss in the middle of a jump/branch would cause a "burp" in your pipeline. Whatever the reason... Alignment of the jump/branch instruction can be done by inserting NOPs or other instructions that do nothing or harmless actions. You could insert jump/branch but then you would have to align those too ;). One popular technique is to insert conditional assembly language instructions that insert NOP padds based on the relative program counter offset. Some assemblers use $ or . as the next code offset. When code segments are aligned on a boundry suitable for your purposes (in this case if on 8, 16, 32, ...) then something like IF $&7 IF $&7 IF $&7 IF $&7 IF $&7 IF $&7 IF $&7 Use whatever the syntax is of the assembler to test the current offset and then based on the test to conditionaly insert some code. Note, if the code generated by the thing you use for NOP is more than 1 byte then making alignment is more of a challenge. e.g. if the next code location is at an odd offset and if the "NOP" is 2 bytes then you will never get into alignment by padding with that. To fix this your "uggly" code will get ugglier. As this may require a harmless instruction that consumes an odd number of bytes. If the alignment is for page fault and not cache miss then you would want to change the conditions such that if the jump/branch wouild be split across a page boundry then insert the padds. IF (($&0FFF)+7)&01000) IF $&7 Or something to that effect assuming 4KB page size. If using gcc then modifying the compiler would be the way to go. Then your source code would not require the uggly necessities (and would not requre changes later should this requirement be lifted). Jim Dempsey ----- Original Message ----- From: "Matjaz Breskvar" phoenix@opencores.org> To: openrisc@opencores.org> Sent: Wednesday, February 25, 2004 5:55 PM Subject: [openrisc] gcc instruction align
targets)

* Jim Dempsey (tapedisk@ameritech.net) wrote:

you guessed right. i want to avoid cases where delay slot is first
instruction on page (and thats the same as jump/branch beeing the last).

(all openrisc instructions are 4 bytes so aligment of all jumps to 8 would
do. even better would be to only insert one NOP before jumps/branches
at the end of the page)



fortunately this is not the case ;)



yes exacly. i would do this only if it's relativly small change to
compiler. so before i dive in i wanted to ask if someone would
have any ideas or perhaps did something similar in gcc...

best regards,
p.

----- Original Message ----- From: "Matjaz Breskvar" phoenix@opencores.org> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Friday, February 27, 2004 7:23 PM Subject: Re: [openrisc] gcc instruction align
Let me rephrase in more precise terms

Due to pipeline design the instruction following the Jump and
Branch instructions are executed. This "following instruction"
is called the Delay Slot. The programmer or compiler has an
option of filling in the Delay Slot with either a useful instruction
or an instruction that effectively performs a NOP.

For reasons yet to be explained I wish to make certain that
the Delay Slot instruction does not begin at the first byte of
a page boundry.

I think that sums it up (except for the technical reasons for why
you need to do this.

Not being familiar with the openrisc instruction set...

Assuming all Jump and Branch instructions are 4 bytes (including any
immediate data) then you need only adjust the assress of the instructions
that have Delay Slots where the Delay Slot falls into the next page.

The following is pseudo code. Rewrite for your environment

#define PAGESIZE 4096
#define myJUMP \
#if(($+4)&(PAGESIZE-1) \
NOP \
#endif \
jump

You would could pass in the page size as a command line argument.
If the page size is not specified then assume smallest possible page
(8, 16, 32, 64, 128, 256, ???)



I haven't seen the innards of gcc but I have maintained many
assemblers, compilers and linkers in my days. In my humble opinion
It should be relatively easy for someone of some competence to
look at how gcc: a) emits code, b) reference the current code offset.
Then find the code sections that deal with instructions that use
delay slots. In there jamb in the NOP. In many cases a compiler
makes a function call passing arguments for code emission. If so
then I would suggest modifying this function to

if(currentLoadPointAtEndOfPage())
{
if(instructionWithDelaySlot(thisInstruction))
{
emit(NOPinstruction); // likely a recursive call
}
}

Jim Dempsey

* Jim Dempsey (tapedisk@ameritech.net) wrote:
Let me rephrase in more precise terms

Due to pipeline design the instruction following the Jump and
Branch instructions are executed. This "following instruction"
is called the Delay Slot. The programmer or compiler has an
option of filling in the Delay Slot with either a useful instruction
or an instruction that effectively performs a NOP.

For reasons yet to be explained I wish to make certain that
the Delay Slot instruction does not begin at the first byte of
a page boundry.

The hardware should work right without the padds,
if not then it should be fixed.

That being said, sometimes when trying to isolate timming issues
I can see the utility of having a means whereby you can eliminate
some circumstances while debugging the processor. (e.g. NOPs).

On the flip side, a good instruction set diagnostic would perform
regression testing of Jump/Branch at all address permutations
(or at least those you could concieve of as having problems).

Permutations of

Jump Delay-Slot Target
In Pipeline
In Cache
Page

And where Page varies in permutation of Banks, type (RAM, ROM, Flash, ...)
And where address change reflect permutations of which bits and how
many bits change in the Jump/Branch.

Added to the Jump test would be extenuating circumstances such as
Jump following various instructions (e.g. reg only, memory read-hit,
memory read-miss, memory write-hit, memory write-miss, port IN
port OUT, on return from interrupt, at moment of interrupt, other...)
as well as the target being those of the type listed.

Then their are diagnostic issues regarding various temp, clock and
voltage settings.

Writing a proper instruction set diagnostic is somewhat of a black
art. Especialy so if the program that detects the problem is also
running in the processor exhibiting the problem.


Jim Dempsey