Hello Helpers, Does any one has already an ALU module imlemented in Verilog HDL. I want to use it as a hint for the ALU I am implementing for my new processor architecture. I have already find an ALU on the Net. But there are some problems I could not undrestand. Especially the STATUS register 's bits setting ( ex. Z, C, N, ..). Thank you so much for your help. /Ben UEC, IS www.uec.ac.jp BEN ABDALLAH ABDERAZEK Assistant Professor in Parallel/Distributed Computer Systems University of Electro-Communications Graduate School of Information Systems 1-5-1 Chofu-shi, Tokyo, Japan Tel: + 81-424 43 5637 fax + 81-424 43 56 81 @-----------------------------------------------------------@ 電気通信大学 大学院 情報システム学研究科 情報ネットワーク学専攻 分散処理学講座 UEC, IS, Sowa Laboratory, Tokyo HP: http://www.sowa.is.uec.ac.jp/ Phone: +81-424-43-5637　 Fax: +81 -424-43-5681 @-----------------------------------------------------------@