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Re: openrisc 1500
by Unknown on Mar 9, 2004 |
Not available! | ||
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Matjaz Breskvar phoenix@opencores.org> wrote:
: * Johan Rydberg (jrydberg@night.trouble.net) wrote:
: > "Damjan Lampret" lampret@opencores.org> wrote:
: >
: > : - there are some bugs I think, at least there were maybe not anymore
: > : (Phoenix?), for example there was one in linker
Can any of you say if this is legal code. It should be, at least
I think so, but I just want to verify.
[It is the result of my split sfCC+bX into sfCC/bX patch]
l.lwz r3,0(r4) # SI load
l.sfnei r3, 0
l.bf .L26 # delay slot filled
l.sfles r8, r6
...
Does the simulator handle this kind of code? If I remember anything
of the simulator internals it should, but things might have changed.
--
Johan Rydberg, Free Software Developer, Sweden
http://rtmk.sf.net | http://www.nongnu.org/guss/
Playing Ratatat - Cherry
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Re: openrisc 1500
by Unknown on Mar 9, 2004 |
Not available! | ||
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* Johan Rydberg (jrydberg@night.trouble.net) wrote:
Matjaz Breskvar phoenix@opencores.org> wrote:
: * Johan Rydberg (jrydberg@night.trouble.net) wrote:
: > "Damjan Lampret" lampret@opencores.org> wrote:
: >
: > : - there are some bugs I think, at least there were maybe not anymore
: > : (Phoenix?), for example there was one in linker
Can any of you say if this is legal code. It should be, at least
I think so, but I just want to verify.
[It is the result of my split sfCC+bX into sfCC/bX patch]
l.lwz r3,0(r4) # SI load
l.sfnei r3, 0
l.bf .L26 # delay slot filled
l.sfles r8, r6
...
Does the simulator handle this kind of code? If I remember anything
of the simulator internals it should, but things might have changed.
that should work. the following snippet is from linux and it causes no problems neither in simulator neither in hw. l.srli r6,r6,26 // check opcode for write access l.sfeqi r6,0 // l.j l.bf 8f l.sfeqi r6,1 // l.jal l.bf 8f l.sfeqi r6,3 // l.bnf l.bf 8f ... regards, p. |
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