I've studied the architecture manual a bit and need some help with figuring out how floating point support really works :) First regarding floating point registers: In section 4.1 : Thirty two or sixteen 32/64-bit general-purpose registers ... Thirty two 64-bit vector/floating point/DSP registers. Later, in section 4.4: The thirty-two general-purpose registers ... are 32 bits wide in 32-bit implementations and 64 bits in 64-bit implementations. They holds scalar integer data, floating-point data, vectors or memory pointers... The GPRs may be accessed as both source and destination registers by ORBIS, ORVDX and ORFPX instructions. So, which is it? Does the architecture have separate floating-point registers, which is always 64-bits wide? Or does it use the GPRs? Second. Reading the documentation of the FP insns you note that single precision is only available on 32-bit implementations and 64-bit implementations have only double precision. Normally you have single precision also when double precision is available. Is there any perticular reason for just having one precision format? I'm currently looking through GCC to see if it is possible to promote all single precision to double precision for the 64-bit case. -- Johan Rydberg, Free Software Developer, Sweden http://rtmk.sf.net | http://www.nongnu.org/guss/ Playing Granada - Beginners