Hello,

I am a university student trying to simulate the or1k using synopsys's
VCS. I have tried going through the hardware tutorial as well as several
other ideas. I do not want to run the processor on an FPGA; I just
want to simulate it. I can get all the verilog code to compile, but my
problem is that I am unclear as to how the or1k begins its first fetch
cycle. I am also unsure of where to put a test (dummy) program in
memory for the or1k to read. Do I need a flash module to boot?
Basically, I cannot jumpstart the processor/wishbone/etc. I am still
new to all of this (obviously), and any help or advice would be much
appreciated. I just need someone to point me in the right direction!

regards,

Charles Stiernberg

Charles, A good way to start is to look at the simulation script for Cadence NCsim. Look at the orp_soc/sim/bin/run_rtl_regression (and run_sw how to build the test cases) regards, Damjan ----- Original Message ----- From: CStiernberg@mail.utexas.edu> To: openrisc@opencores.org> Sent: Monday, March 15, 2004 9:08 AM Subject: [openrisc] or1k/orp_soc VCS simulation

Hello Damjan,

I had tried earlier to study ORP SOC the same way you suggested by
looking at the script.

But, there are many NCsim commands in the script which i don't
understand.

Is there any documentation of script for writing it for other
simulators?

It will be a great help in "tuning" the script for other simulators if u
can paste NCsim help here (atleast the commands used in the script).

Regards,
-Soban.


Damjan Lampret wrote:


--

Soban,

I'm doing essentially the same thing as you except that I am using
cadence tools to simulate the verilog. I haven't been able to get the
cache-based programs to execute correctly (the -icdc) and would be
interested to here if you do get them to succesfully simulate. Also, I
had to change some of the memory settings in the or1200_defines etc.
because I am using generic ram and not anything specific to FPGA technology.

Here's my understanding of what the script does:

set simpletests=(dhry-nocache-O2 dhry-icdc-O2 mmu-nocache mmu-icdc
basic-icdc basic-nocache mul-nocache-O2 mul-icdc-O2)
set complextests=(except-nocache except-icdc cbasic-nocache-O2
cbasic-icdc-O0)
#These tell the simulation what benchmarks to run. It's assumed that
the benchmarks are already compiled properly and in their correct directory.


set simpletimes=(100 100 100 100 40 40 40 40 60 \
40 40 40 40 40 40 40 40 40)
set complextimes=(40 40 40 40 40 40 40 40 40 \
40 40 40 40 40 40 40 40 100 \
40 40 \
40 40 \
40 40 \
40 40)
#These tell the simulation how much simulation time to give each
benchmark (in simulated milliseconds) I haven't figured out why the
different values are used as most of the benchmarks I simulate complete
easily within the given time.


# Process arguments
if ($1 == "simple") then
set tests=(${simpletests})
...
# This section just processes any command line inputs given to the script


# List all selected tests
...
# Should be obvious...



# Prepare all .args files
iteration:
echo ""
echo "echo "echo "if (${iterations[$iter]} != "") then
ncprep +define+${iterations[$iter]} -f ${nc_args} > ncprep.out
else
ncprep -f ../bin/nc.scr > ncprep.out
endif
if (`tail -1 ncprep.out | grep Failed` != "") then
echo ""
cat ncprep.out
exit
endif
# This prepares for the compilation step by processing all the included
directories and files provided in nc.scr. This is a necessary step for
the cadence compiler.


# Run NC-Verilog compiler
echo ""
echo "\\t@@@"
echo "\\t@@@ Compiling sources"
echo "\\t@@@"
ncvlog -NOCOPYRIGHT -f ncvlog.args > ncvlog.out
if ($status != 0) then
echo "\\t@@@ FAILED"
echo ""
cat ncvlog.out
exit
else
echo "\\t@@@ Passed"
endif
# Compile all the verilog files and libraries used


# Run the NC-Verilog elaborator (build the design hierarchy)
echo ""
echo "\\t@@@"
echo "\\t@@@ Building design hierarchy (elaboration)"
echo "\\t@@@"
ncelab -NOTIMINGCHECKS -NOCOPYRIGHT -f ncelab.args > ncelab.out
if ($status != 0) then
echo "\\t@@@ FAILED"
echo ""
cat ncelab.out
exit
else
echo "\\t@@@ Passed"
endif
# Elaborate the design. (This is somewhat synonymous to linking and
loading in a C-compiler)


#The next part sets up a loop for each iteration and for each benchmark.
...


# Run the NC-Verilog simulator (simulate the design)
sim:
set i = 0;
foreach test ($tests)
...
# Simulate each benchmark and check for correct execution by looking at
the resulting register trace for the "deaddead" values.
# Note the "cp ../src/${test}.hex ../src/flash.in" line
# This copies the binary (in ASCII hex format) from the compiled source
file to the flash.in file which is used by $readmemh to load the program
into simulated flash memory.


Hope this helps.
If you do get a general script written that works under Synopsys, you
may want to submit it so others can benefit from it.

--Chris

Soban Shoeb Chawre wrote:

Soban, if you can wait, I'm currently working on making the simulation script much simpler. Basically the new test environment will no longer use the script to run different test cases, but will be just execute a single simulation and within that single simulation test bench will load different test cases. I think this will have significant impact on running the whole thing on other simulators. And since I will be commiting in a new test environment this also means there will be some new test cases that I have made (among other a test bench for the new HW breakpoints support). We will see if I can have it done over the week end. I'll also look at the icdc that somebody else reported. I think there is a bug when WB clocks are 1/2 of the main clock. Fortunately I don't know anybody using it in this kind of configuration (WB interfaces at 1/2 main RISC clock). regards, Damjan ----- Original Message ----- From: "Soban Shoeb Chawre" sobanc@nital.stpp.soft.net> To: "List about OpenRISC project" openrisc@opencores.org> Sent: Wednesday, March 17, 2004 7:24 AM Subject: Re: [openrisc] or1k/orp_soc VCS simulation