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Some OR questions
by PaulTaylor on Mar 31, 2004 |
PaulTaylor
Posts: 1 Joined: Jul 2, 2020 Last seen: Jul 9, 2026 |
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Hi,
I'm considering using OR1200 or OR1100 processor in an FPGA design, and I'm just trying to get an idea of the things I need to do to get a system working. I have done a lot of FPGA design in the past, but not much in the last couple of years. My questions are: (1) I have downloaded docs regarding OR1200, but I think the OR1100 might be better for me as it has no cache + no mmu. Does the OR1100 exist yet, and work? (I noted that a roadmap suggested 2003 completion for this design). Are there any docs on the OR1100? Or is it a case of using the 1200 docs and ignoring the cache/mmu specifics? (2) If the 1100 does exist, how much resources does the design need compared to the OR1200? I noticed that the OR1200 takes about 3000 slices in a Xilinx device. I am trying to figure out how much resource the processor would take. (3) I will be putting the processor into a Xilinx sparten FPGA, with a UART + memory controller (for 1MByte of SRAM and 1MByte of Flash). Eventually, I want to put the opencore's ethernet controller into the device as well. Could anyone give me some clues as to what sort of size FPGA I should be aiming for, so that the design would compile relatively easily. (4) Can the above be done using Xilinx Webpack, or do I need one of Xilinx's other offerings. If anyone can answer one or a multiple of the above questions, I'd be most grateful. Regards, Paul. |
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Some OR questions
by Unknown on Apr 1, 2004 |
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Hi Paul,
there is no such thing as OR1100. However OR1200 has been enhanced to be
fully configurable including selection of MMUs/caches. For example you can
remove just the MMUs (either DMMU or IMMU or both) and keep caches. Or
remove also the caches, either icache, dache or both etc. Basically I would
suggest to look at or1200_defines.v and read it. All configuration options
are explained. Speed and size for Virtex FPGAs assumes maximum configuration
(all options enabled).
http://www.opencores.org/cvsweb.shtml/or1k/or1200/rtl/verilog/or1200_defines.v?rev=1.35.4.6&content-type=text/x-cvsweb-markup&only_with_tag=rel_26
I suggest you use "rel_26" release because it also has some features not
found in the main branch (like embedded RAM for data/insn)
regards,
Damjan
----- Original Message -----
From: "Paul Taylor" pault.ngea@virgin.net>
To: openrisc@opencores.org>
Sent: Wednesday, March 31, 2004 8:42 PM
Subject: [openrisc] Some OR questions
Hi,
I'm considering using OR1200 or OR1100 processor in an FPGA design, and
I'm just trying to get an idea of the things I need to do to get a
system working. I have done a lot of FPGA design in the past, but not
much in the last couple of years. My questions are:
(1) I have downloaded docs regarding OR1200, but I think the OR1100
might be better for me as it has no cache + no mmu. Does the OR1100
exist yet, and work? (I noted that a roadmap suggested 2003 completion
for this design). Are there any docs on the OR1100? Or is it a case of
using the 1200 docs and ignoring the cache/mmu specifics?
(2) If the 1100 does exist, how much resources does the design need
compared to the OR1200? I noticed that the OR1200 takes about 3000
slices in a Xilinx device. I am trying to figure out how much resource
the processor would take.
(3) I will be putting the processor into a Xilinx sparten FPGA, with a
UART + memory controller (for 1MByte of SRAM and 1MByte of Flash).
Eventually, I want to put the opencore's ethernet controller into the
device as well. Could anyone give me some clues as to what sort of size
FPGA I should be aiming for, so that the design would compile relatively
easily.
(4) Can the above be done using Xilinx Webpack, or do I need one of
Xilinx's other offerings.
If anyone can answer one or a multiple of the above questions, I'd be
most grateful.
Regards,
Paul.
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http://www.opencores.org/mailman/listinfo/openrisc
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