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jp1.c problem
by Unknown on Apr 15, 2004 |
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Hi
I have read your opeisc-SW-tutorial.pdf from Dries's website.It is really good for me.I have run“./jp1-xilinx 9999”and met the problem like the following of the pdf file: problem: ‘Read’ and ‘Expected’ values only sometimes differ advice: check the OR1200 core itself, more specifically check the timing of the ALU registers. I don't know how to solve the problem. Should I change the verilog code of ALU? and how? Thanks and Regards |
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jp1.c problem
by Unknown on Apr 15, 2004 |
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No you shouldn't change the Verilog code, just make sure your design when
implemented in the FPGA meets all your timing constraints for the given
clock. If it doesn't, reduce the clock frequency on your FPGA board.
regards,
Damjan
----- Original Message -----
From: 305liuzg@163.net>
To: openrisc@opencores.org>
Sent: Thursday, April 15, 2004 6:07 PM
Subject: [openrisc] jp1.c problem
Hi
I have read your opeisc-SW-tutorial.pdf from Dries's website.It is really
good for me.I have run“./jp1-xilinx 9999”and met the problem like the
following of the pdf file:
problem: ‘Read’ and ‘Expected’ values only sometimes differ
advice: check the OR1200 core itself, more specifically check the timing
of the ALU registers.
I don't know how to solve the problem.
Should I change the verilog code of ALU?
and how?
Thanks and Regards
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
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