Hi everyone!!!

I´m implementing a PROCESSOR in VHDL, but I have a problem when I try
to connect the componets in my top file. The problem is when I assign
many sources at one signal(on the Port Map), i.e. My signals are
conected at one bus. like this::

U1: instreg PORT MAP( opcode => opcode,datain => bus, DIRout => buss,
Kout => buss, dataout => buss, etc.....);

U2: proc PORT MAP(datain => buss, dataout => buss, etc....);

I also read that I can implement a Resolution Functions to solve this
problem, but You know, the resolution function is not supported for
Max-Plus II. ....

does everybody know how I can solve this problem or know other way to
implement it?

I used MaxPlus and FPGA from ALTERA,
thanks in advance
best regards

JLuis
MÉXICO

Hello,

maybe you are falling into a VHDL concept error, are you using
inout signals and assigning Z to them anytime but when you do know
which component has to write to it (remember only one can write at a
given time!)? Anyways, it is difficult to help you if you don't say
what is the error that MAXPLUS is giving you! Post a message with the
output. Regards,

Victor Lopez
SPAIN

Just in case you have problems reading English here is the message in
Spanish (I put it in English first for respect to the mailing-list
users):

Hola,

tal vez estés cayendo en un error de concepto de VHDL, usas señales
inout y les asignas Z en todo momento salvo cuando sabes que tienes que
escribir un valor determinado por parte de un componente (recuerda que
solo uno puede escribir en un instante dado!)? De todas formas, es
dificil poder ayudarte si no dices cual es el error que MAXPLUS te está
dando! Pon un mensaje con la salida del programa. Saludos.