Hi all, I am planning to do some changes to the rtl code of openrisc just playing around a little. I am able to do run_rtl_regression and the tests are compiling/running fine. it says test passed. I am not sure how the script concludes that the certain test has "passed" or "failed" based on what was written in the general.log file. The general.log file is written into by or1200_monitor.v which is a simulation monitor. Could someone please explain this process..of how or1200_monitor works and how whether or not a test is passed or failed is established. I wanted to compile and run some of my own code..and was wondering how one should check for correctness? I mean when my code runs on an actual machine I can used printfs to sort of guide me throught debugging the expected output..how do I do this when I run my code on a verilog simulation. Hope I get some replies this time :| Thanks! LEARNER __________________________________ Do you Yahoo!? Yahoo! Photos: High-quality 4x6 digital prints for 25¢ http://photos.yahoo.com/ph/print_splash