Hello:

When I generate memories with coregen using ISE 6.1i they have not
the same pins as the ones in OR1200 files. Which version of ISE are
you using?

Regards

Javier Castillo

I don't know who are you asking, but I use Synplify for synthesis and ISE for P&R. Xilinx RAMs supported are fro mthe Virtex family, I think they might be supported by Virtex II as well by means of automapping in ISE although true Virtex II RAMs have different names than on OR1200. So somebody might want to update OR1200 RAMs by adding additional FPGA families - that is in fact why RAM instantiation files are separated so they can easily be updated to support other FPGA families and other ASIC libraries. regards, Damjan ----- Original Message ----- From: jcastillo@escet.urjc.es> To: openrisc@opencores.org> Sent: Friday, May 21, 2004 7:10 PM Subject: [openrisc] Coregen memories and ISE version