Hi, I am using FPGA compiler II to generate net list of a Verilog module. The module can be compiled without any error and I can find the Est. Frequency from the optimized chips. I want to know is it possible to know also the number of gates? If it is not possible, is there are any additional or other tools i can use to find the number of gates of a synthesized module. Regards, Ben IS-N -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/openrisc/attachments/20040527/a87db2c8/attachment.htm