hi all,
i am synthesizing a design using synplify_pro. i need to
specify one of the paths as a multicycle path. i have read that
define_multicycle_path attribute is used to do this. but i dont know
how to use it in a hierachical design. i mean the signals between
which i need to have a multicycle path are not in the top module but
in some module down the order. so how do i do it. does anyone have a
clue about it ? please let me knoe. its urgent.

thanks
hemant

Hi,

i am not very profficient with this but I've been told that
retiming could be used for that. Let's say that you have a multiplier
unit that you want implemented as a multicycle operation one solution
is to have it in one module and specifying the multiply to last one
cycle (only one clock'event and ...) and then putting some more empty
(clock'event and...) as many as cycles you would want your
implementation to take, and then synthesize with Synplify activating
the "Retiming" option (it is a checkbox in the main window), what it
does is to merge the flip-flops specified by the empty clock'events
with the multiplication hardware, actually making it a pipelined
multiplier, but the results may not be as good as you would expect.
Another solution is to break the algorithm that you want to make
multicycle and pipeline it manually, this last one is more complex but
far more educative and lets you decide what's going on and to see where
the biggest burden to execution time is. I've personally never tried
the retiming option but have been told to work as I've said, though
you'd better take a look at the help files to have a more insight
explanation of it. Hope it helped, best regards,

Víctor López