Hi.

I showed off the OR1200 at the Design Automation Conference last week.
I think many people there were quite interested in the OR1200 (which
made it a good demo for our stuff). I also used it in a Structured ASIC
tutorial I gave on Thursday, which had 16 people.

I used a 4K instruction and data caches, and turned off both MMUs, and
QMEM. There was still a ton of SRAM on the 9x10 ViaMask base available,
but I wanted the whole CPU (with memory) to fit in one corner of the
array.

I'll talk to my boss about giving out more detailed results (area,
timing, etc). A bunch of guys copied down the data they saw on the
screen, so I think the info is already in the hands of our competitors.

While I'm not much of an HDL designer, I was impressed by the quality of
the code in the OR1200. I had very little difficulty using it. Thanks
to the authors for making it available.

Bill