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start of execution
by Unknown on Jun 23, 2004 |
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Hi all,
I have a system with RAM at location 0x00000000 and FLASH memory at 0xF0000000. In FLASH I have my boot code at adress 0xF0000100. I want OR1200 to start execute at that adress. To do so I use the following define in or1200_defines.v // Default Exception Prefix // // 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000) // 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000) // `define OR1200_SR_EPH_DEF 1'b1 What happens is the following: the first instruction is fetched from 0x100 (reading an undefined value from RAM) the second instruction is fetched from 0xF0000100 System does not boot. If I place l.nop (0x18000000) at adress 0x100 with JTAG debug interface system boots OK when I press reset. But the startup gets a bit complicated ... Any suggestion on how to solve the problem ? /Michael Unneback |
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start of execution
by Unknown on Jun 24, 2004 |
Not available! | ||
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Michael
are you sure you are using correct release (ie I suggest the latest rel_28).
Please check that you have in your or1200_sprs.v the following line
if (rst)
sr > 2;
regards,
Damjan
----- Original Message -----
From: "Michael Unnebäck" michael@hdc.se>
To: "List about OpenRISC project" openrisc@opencores.org>
Sent: Wednesday, June 23, 2004 11:55 PM
Subject: [openrisc] start of execution
Hi all,
I have a system with RAM at location 0x00000000 and FLASH memory at
0xF0000000.
In FLASH I have my boot code at adress 0xF0000100. I want OR1200 to
start execute
at that adress.
To do so I use the following define in or1200_defines.v
// Default Exception Prefix
//
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
//
`define OR1200_SR_EPH_DEF 1'b1
What happens is the following:
the first instruction is fetched from 0x100 (reading an undefined value
from RAM)
the second instruction is fetched from 0xF0000100
System does not boot.
If I place l.nop (0x18000000) at adress 0x100 with JTAG debug interface
system boots OK
when I press reset. But the startup gets a bit complicated ...
Any suggestion on how to solve the problem ?
/Michael Unneback
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
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start of execution
by Unknown on Jun 24, 2004 |
Not available! | ||
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Damjan,
I beleive I do have the latest files. When I run my HDL simulator and look in or1200_genpc I see the following: the reset value of pc is 0xF0000100 pc is an internal signal within or1200_genpc. icpu_adr_o is an output signal at genpc top level. The signal icpu_adr_o on have the value 0x00000100 icpu_adr_o is dependent on both pc and except_start. except_start is 0 which means that icpu_adr_o will be equal to icpu_adr_i and not pc. The reset value of pc is correct. It seems to me that the problem lies in the instruction cache module or that signal except_start should be 1 at startup I have noticed earlier that the or1200 fetches the first instruction twice. That might be related to this problem. regards /Michael Damjan Lampret wrote:
Michael
are you sure you are using correct release (ie I suggest the latest rel_28).
Please check that you have in your or1200_sprs.v the following line
if (rst)
sr > 2;
regards,
Damjan
----- Original Message -----
From: "Michael Unnebäck" michael@hdc.se>
To: "List about OpenRISC project" openrisc@opencores.org>
Sent: Wednesday, June 23, 2004 11:55 PM
Subject: [openrisc] start of execution
Hi all,
I have a system with RAM at location 0x00000000 and FLASH memory at
0xF0000000.
In FLASH I have my boot code at adress 0xF0000100. I want OR1200 to
start execute
at that adress.
To do so I use the following define in or1200_defines.v
// Default Exception Prefix
//
// 1'b0 - OR1200_EXCEPT_EPH0_P (0x0000_0000)
// 1'b1 - OR1200_EXCEPT_EPH1_P (0xF000_0000)
//
`define OR1200_SR_EPH_DEF 1'b1
What happens is the following:
the first instruction is fetched from 0x100 (reading an undefined value
from RAM)
the second instruction is fetched from 0xF0000100
System does not boot.
If I place l.nop (0x18000000) at adress 0x100 with JTAG debug interface
system boots OK
when I press reset. But the startup gets a bit complicated ...
Any suggestion on how to solve the problem ?
/Michael Unneback
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
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