Hi all,

I do a minor patch on the or1200_genpc.v file. In the original code, the asynchronous
reset of 'pcreg' is not a constant value. It's rely on the signal 'except_prefix', but the
signal will set a value when it's on the reset period. In our design rule, we do not
permit gating the asynchronous reset signal with any others signal. I change the code to
the following patch. I think it's the equivalent of original code.

I am not familiar with Verilog, I do all of the design with VHDL. In fact, I don't know
the patch is right or not. Dose any one have suggestion?

Thanks of all.
Kuoping

--- or1200_genpc.v.orig Wed Jun 30 18:00:21 2004
+++ or1200_genpc.v Wed Jun 30 18:01:30 2004
@@ -309,7 +309,7 @@
always @(posedge clk or posedge rst)
if (rst)
// pcreg - pcreg `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
+ pcreg `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
else if (spr_pc_we)
pcreg else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i &
!genpc_refetch)
// else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
pcreg