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problem with clk signals
by Unknown on Jul 14, 2004 |
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Dear All,
I try to implement a Soc to my FPGA panel and the ISA 6.1 find some clk-D type flip flop error in the immu and the pm module. I don't know how can I solve the problem. If somebody know the answare please write to me. Thank you very much. Erno Below the the error code: ERROR:NgdBuild:466 - input pad net 'clk' has illegal connection. Possible pins causing this are: pin C on block or1200_top_or1200_pm_sdf_2 with type FDCE, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_27 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_28 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_29 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_31 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_30 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_0 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_1 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_2 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_3 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_4 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_5 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_6 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_7 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_8 with type FDP, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_9 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_10 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_11 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_12 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_13 with type FDC WARNING:NgdBuild:479 - The input pad net 'tdmrx' is driving one or more clock loads that should only use a dedicated clock buffer. This could result in large clock skews on this net. Check whether the correct type of BUF is being used to drive the clock buffer. NGDBUILD Design Results Summary: Number of errors: 1 Number of warnings: 1 Total memory usage is 48940 kilobytes One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "xsv_fpga_top.bld"... ERROR: NGDBUILD failed Process "Translate" did not complete. |
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problem with clk signals
by Unknown on Jul 16, 2004 |
Not available! | ||
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Hi Erno,
a solution can be remove completely the ISE 6.1 software, and
reinstall it. We found that previous Webpack might cause such errors
(it is not sure), but the problem disappeared.
peter
ps: the idea came from that exactly the same project file was error
free on another PC.
----- Original Message -----
From: verno@a...verno@a...>
To:
Date: Wed Jul 14 17:48:53 CEST 2004
Subject: [openrisc] problem with clk signals
Dear All,
I try to implement a Soc to my FPGA panel and the ISA 6.1 find some clk-D type flip flop error in the immu and the pm module. I don't know how can I solve the problem. If somebody know the answare please write to me. Thank you very much. Erno Below the the error code: ERROR:NgdBuild:466 - input pad net 'clk' has illegal connection. Possible pins causing this are: pin C on block or1200_top_or1200_pm_sdf_2 with type FDCE, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_27 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_28 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_29 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_31 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_30 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_0 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_1 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_2 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_3 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_4 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_5 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_6 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_7 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_8 with type FDP, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_9 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_10 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_11 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_12 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_13 with type FDC WARNING:NgdBuild:479 - The input pad net 'tdmrx' is driving one or more clock loads that should only use a dedicated clock buffer. This could result in large clock skews on this net. Check whether the correct type of BUF is being used to drive the clock buffer. NGDBUILD Design Results Summary: Number of errors: 1 Number of warnings: 1 Total memory usage is 48940 kilobytes One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "xsv_fpga_top.bld"... ERROR: NGDBUILD failed Process "Translate" did not complete. |
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problem with clk signals
by Unknown on Jul 20, 2004 |
Not available! | ||
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Dear All,
I haven't solved the following problem with the ISE 6.1. I'd like to inquire: Has anybody the same problem with the orp Soc. Has anybady a good ide how can I solv the following problem? Thanks a lot! Erno Varga
Below the the error code:
ERROR:NgdBuild:466 - input pad net 'clk' has illegal connection. Possible pins causing this are: pin C on block or1200_top_or1200_pm_sdf_2 with type FDCE, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_27 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_28 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_29 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_31 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_30 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_0 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_1 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_2 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_3 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_4 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_5 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_6 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_7 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_8 with type FDP, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_9 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_10 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_11 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_12 with type FDC, pin C on block or1200_top_or1200_immu_top_icpu_adr_o_13 with type FDC WARNING:NgdBuild:479 - The input pad net 'tdmrx' is driving one or more clock loads that should only use a dedicated clock buffer. This could result in large clock skews on this net. Check whether the correct type of BUF is being used to drive the clock buffer. NGDBUILD Design Results Summary: Number of errors: 1 Number of warnings: 1 Total memory usage is 48940 kilobytes One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "xsv_fpga_top.bld"... ERROR: NGDBUILD failed Process "Translate" did not complete. |
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