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jp1 server by Unknown on Jul 23, 2004			Not available!
Dear All, I try to implement a little SoC to a MEMEC board with Virtex xcIIv1000. I use the ORP base verilog code. I chopped so many modules. On my Soc there is the or1k, debug unit, uart and cop matrix. I tried to communicate throu the jp1 server but unfortunately a I couldn't. I get this message : Connected to parallel port at 378 I read the forum in same subject and found that: I have to check the jtag connection. I have done it but the problem hasen't solved yet. I connect the debug unit jtag port to the jtag unit which is on the paralel cable. I checked the signals with an oscilloscope there are on the jtag unit pins. I hope these signals are correct and timing is ok. On the board there is a 24MHz clock and I use it as input clk. This frequency is good or too high? On my jtag module there isn't trst signal. Is it necessary to the connection or is it enough to put it to a switch on the board and push before the server starts? If I use just some modules (or1k,debug unit, uart, cop matrix) the jp1 server could communicate the Soc? How can I check the jtag unit pin signals are correct, what I have to watch on the oscilloscop in each pin? If somebody could anwser my questions thanks a lot. Erno Varga Dear All, I try to implement a little SoC to a MEMEC board with Virtex xcIIv1000. I use the ORP base verilog code. I chopped so many modules. On my Soc there is the or1k, debug unit, uart and cop matrix. I tried to communicate throu the jp1 server but unfortunately a I couldn't. I get this message : Connected to parallel port at 378 I read the forum in same subject and found that: I have to check the jtag connection. I have done it but the problem hasen't solved yet. I connect the debug unit jtag port to the jtag unit which is on the paralel cable. I checked the signals with an oscilloscope there are on the jtag unit pins. I hope these signals are correct and timing is ok. On the board there is a 24MHz clock and I use it as input clk. This frequency is good or too high? On my jtag module there isn't trst signal. Is it necessary to the connection or is it enough to put it to a switch on the board and push before the server starts? If I use just some modules (or1k,debug unit, uart, cop matrix) the jp1 server could communicate the Soc? How can I check the jtag unit pin signals are correct, what I have to watch on the oscilloscop in each pin? If somebody could anwser my questions thanks a lot. Erno Varga

jp1 server by Unknown on Jul 23, 2004			Not available!
[q] If I use just some modules (or1k,debug unit, uart, cop matrix) the jp1[/q] server could [q] communicate the Soc?[/q] Yes or1k and debug are enough to connect jp1 / gdb. There are two versions of debug, one that works with jp1 and one that works with jp2. Make sure you use the right one. The tutorial is for jp1 (but the concept is the same for jp2) <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf">http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf</A> <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf">http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf</A> regards, Damjan If I use just some modules (or1k,debug unit, uart, cop matrix) the jp1 server could communicate the Soc? Yes or1k and debug are enough to connect jp1 / gdb. There are two versions of debug, one that works with jp1 and one that works with jp2. Make sure you use the right one. The tutorial is for jp1 (but the concept is the same for jp2) http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf regards, Damjan

jp1 server by Unknown on Jul 26, 2004			Not available!
Dear Damjan, Thank you your quick anwser. I have read the hardware and software tutorial and followed the directions, but unfortunately the jp1 server couldn't communicate with the SoC. I read the the jp1.c file and found that in xilinx mode it isn't use the trst_pad_i, but on the dbg_top.v there is a trst signal. I put the trst signal to switch which is on the board and before I use the jp1 software push the reset button is it good method or not? The ISE write: the application could work up to 50MHz, so I just put the clk signal to the MEMEC board 24MHz signal. The WISHBONE_clk and the clk is the same in my SoC. I'm not use the ibufg modul (if I use the ISE write an error ngdbuild 466 ) and not use the CLKDLL. On the HW tutorial there is an instruction remove .genpc_stop_prefetch (genpc_stop_prefetch) the line from the or1200_cpu.v, the newest ORP there isn't a line like this .genpc_stop_prefetch (1'b0) is it good or I have to remove it? I measured the jtag module signals with an oscilloscope and sometimes the clk signal isn't go to the 3,3V peak just approximateli 1,7V is it a normal or my jtag module isn't work properly? Thank you your anwser! Best regards Erno Varga ----- Original Message ----- From: Damjan Lampret<<A HREF="mailto:damjanl@o...">damjanl@o...</A>> To: Date: Fri Jul 23 17:35:31 CEST 2004 Subject: [openrisc] jp1 server [q]> If I use just some modules (or1k,debug unit, uart, cop matrix) [/q] the jp1 server could [q]> communicate the Soc? [/q] Yes or1k and debug are enough to connect jp1 / gdb. There are two versions of debug, one that works with jp1 and one that works with jp2. Make sure you use the right one. The tutorial is for jp1 (but the concept is the same for jp2) <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf">http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf</A> <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf">http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf</A> regards, Damjan [/q] Dear Damjan, Thank you your quick anwser. I have read the hardware and software tutorial and followed the directions, but unfortunately the jp1 server couldn't communicate with the SoC. I read the the jp1.c file and found that in xilinx mode it isn't use the trst_pad_i, but on the dbg_top.v there is a trst signal. I put the trst signal to switch which is on the board and before I use the jp1 software push the reset button is it good method or not? The ISE write: the application could work up to 50MHz, so I just put the clk signal to the MEMEC board 24MHz signal. The WISHBONE_clk and the clk is the same in my SoC. I'm not use the ibufg modul (if I use the ISE write an error ngdbuild 466 ) and not use the CLKDLL. On the HW tutorial there is an instruction remove .genpc_stop_prefetch (genpc_stop_prefetch) the line from the or1200_cpu.v, the newest ORP there isn't a line like this .genpc_stop_prefetch (1'b0) is it good or I have to remove it? I measured the jtag module signals with an oscilloscope and sometimes the clk signal isn't go to the 3,3V peak just approximateli 1,7V is it a normal or my jtag module isn't work properly? Thank you your anwser! Best regards Erno Varga ----- Original Message ----- From: Damjan Lampretdamjanl@o...> To: Date: Fri Jul 23 17:35:31 CEST 2004 Subject: [openrisc] jp1 server > If I use just some modules (or1k,debug unit, uart, cop matrix) the jp1 server could > communicate the Soc? Yes or1k and debug are enough to connect jp1 / gdb. There are two versions of debug, one that works with jp1 and one that works with jp2. Make sure you use the right one. The tutorial is for jp1 (but the concept is the same for jp2) http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf regards, Damjan

jp1 server by Unknown on Jul 27, 2004			Not available!
----- Original Message ----- From: <<A HREF="mailto:verno@analogic-computers.com">verno@analogic-computers.com</A>> To: <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Monday, July 26, 2004 6:09 PM Subject: Re: [openrisc] jp1 server [q] Dear Damjan, Thank you your quick anwser. I have read the hardware and software[/q] tutorial and [q] followed the directions, but unfortunately the jp1 server couldn't[/q] communicate with [q] the SoC. I read the the jp1.c file and found that in xilinx mode it isn't[/q] use the [q] trst_pad_i, but on the dbg_top.v there is a trst signal. I put the trst[/q] signal to switch [q] which is on the board and before I use the jp1 software push the reset[/q] button is it [q] good method or not?[/q] Yes it should be OK. [q] The ISE write: the application could work up to 50MHz, so I just put the[/q] clk signal [q] to the MEMEC board 24MHz signal. The WISHBONE_clk and the clk is the same in my SoC. I'm not use the ibufg modul (if I use the ISE write an error[/q] ngdbuild [q] 466 ) and not use the CLKDLL. On the HW tutorial there is an instruction remove .genpc_stop_prefetch (genpc_stop_prefetch) the line from the or1200_cpu.v, the newest ORP there[/q] isn't [q] a line like this .genpc_stop_prefetch (1'b0) is it good or I have to[/q] remove it? You can ignore this. There used to be unused port definition genpc_stop_prefetch and some synthesis tools had problems with unsused ports. It is no longer there so don't worry about it. [q] I measured the jtag module signals with an oscilloscope and sometimes the[/q] clk [q] signal isn't go to the 3,3V peak just approximateli 1,7V is it a normal or[/q] my jtag [q] module isn't work properly?[/q] It is rather low. Check your datasheet for the FPGA what is the lowest VIH level for clock input. BTW make sure your clock inputs of SOC are using clock inputs of FPGA. regards, Damjan [q] Thank you your anwser! Best regards Erno Varga ----- Original Message ----- From: Damjan Lampret<<A HREF="mailto:damjanl@o...">damjanl@o...</A>> To: Date: Fri Jul 23 17:35:31 CEST 2004 Subject: [openrisc] jp1 server [q] > If I use just some modules (or1k,debug unit, uart, cop matrix)[/q] > the jp1 > server could [q] > communicate the Soc?[/q] > Yes or1k and debug are enough to connect jp1 / gdb. > There are two versions of debug, one that works with jp1 and one > that works > with jp2. Make sure you use the right one. The tutorial is for jp1 > (but the > concept is the same for jp2) > <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf">http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf</A> > <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf">http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf</A> > regards, > Damjan > >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> [/q] ----- Original Message ----- From: verno@analogic-computers.com> To: openrisc@opencores.org> Sent: Monday, July 26, 2004 6:09 PM Subject: Re: [openrisc] jp1 server Dear Damjan, Thank you your quick anwser. I have read the hardware and software tutorial and followed the directions, but unfortunately the jp1 server couldn't communicate with the SoC. I read the the jp1.c file and found that in xilinx mode it isn't use the trst_pad_i, but on the dbg_top.v there is a trst signal. I put the trst signal to switch which is on the board and before I use the jp1 software push the reset button is it good method or not? Yes it should be OK. The ISE write: the application could work up to 50MHz, so I just put the clk signal to the MEMEC board 24MHz signal. The WISHBONE_clk and the clk is the same in my SoC. I'm not use the ibufg modul (if I use the ISE write an error ngdbuild 466 ) and not use the CLKDLL. On the HW tutorial there is an instruction remove .genpc_stop_prefetch (genpc_stop_prefetch) the line from the or1200_cpu.v, the newest ORP there isn't a line like this .genpc_stop_prefetch (1'b0) is it good or I have to remove it? You can ignore this. There used to be unused port definition genpc_stop_prefetch and some synthesis tools had problems with unsused ports. It is no longer there so don't worry about it. I measured the jtag module signals with an oscilloscope and sometimes the clk signal isn't go to the 3,3V peak just approximateli 1,7V is it a normal or my jtag module isn't work properly? It is rather low. Check your datasheet for the FPGA what is the lowest VIH level for clock input. BTW make sure your clock inputs of SOC are using clock inputs of FPGA. regards, Damjan Thank you your anwser! Best regards Erno Varga ----- Original Message ----- From: Damjan Lampretdamjanl@o...> To: Date: Fri Jul 23 17:35:31 CEST 2004 Subject: [openrisc] jp1 server > If I use just some modules (or1k,debug unit, uart, cop matrix) > the jp1 > server could > communicate the Soc? > Yes or1k and debug are enough to connect jp1 / gdb. > There are two versions of debug, one that works with jp1 and one > that works > with jp2. Make sure you use the right one. The tutorial is for jp1 > (but the > concept is the same for jp2) > http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf > http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf > regards, > Damjan > > _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

jp1 server by Unknown on Jul 30, 2004			Not available!
Dear Damjan, Thank you your help, the jp1 server works, there was a problem with the jtag negated reset and the jtag module. The next step is the hello word implementation, I checked and correct the hello.c, board.h, and ram.ld like the SW tutorial. board.h and ram.ld there are some differences because on my SoC there are IC and DC and the onchip ram is smaller (2k) than the example. I make the hello.or32 and start the gdb, but when I write the following instruction:target jtag <A HREF="jtag://localhost:9999">jtag://localhost:9999</A> I get an error message: Unable to set flags for JTAG proxy socket 5 to value 0x401d79c0 I don't know what cause these problem, I think it's free from the hello word c files, maybe the gdb installation is wrong but I followed the toolchain instructins (I use Mandrake Linux)? I have to start the jp1 server before run the gdb or not? Thank yuo your kindness! Best regards! Erno Varga ----- Original Message ----- From: Damjan Lampret<<A HREF="mailto:damjanl@o...">damjanl@o...</A>> To: Date: Tue Jul 27 04:22:54 CEST 2004 Subject: [openrisc] jp1 server [q] ----- Original Message ----- From: <<A HREF="mailto:verno@a...">verno@a...</A>> To: <<A HREF="mailto:openrisc@o...">openrisc@o...</A>> Sent: Monday, July 26, 2004 6:09 PM Subject: Re: [openrisc] jp1 server [q]> Dear Damjan, > Thank you your quick anwser. I have read the hardware and [/q] software tutorial and [q]> followed the directions, but unfortunately the jp1 server [/q] couldn't communicate with [q]> the SoC. I read the the jp1.c file and found that in xilinx [/q] mode it isn't use the [q]> trst_pad_i, but on the dbg_top.v there is a trst signal. I put [/q] the trst signal to switch [q]> which is on the board and before I use the jp1 software push [/q] the reset button is it [q]> good method or not? [/q] Yes it should be OK. [q]> The ISE write: the application could work up to 50MHz, so I [/q] just put the clk signal [q]> to the MEMEC board 24MHz signal. The WISHBONE_clk and the clk [/q] is the same [q]> in my SoC. I'm not use the ibufg modul (if I use the ISE write [/q] an error ngdbuild [q]> 466 ) and not use the CLKDLL. > On the HW tutorial there is an instruction remove [/q] .genpc_stop_prefetch [q]> (genpc_stop_prefetch) the line from the or1200_cpu.v, the [/q] newest ORP there isn't [q]> a line like this .genpc_stop_prefetch (1'b0) is it good or I [/q] have to remove it? You can ignore this. There used to be unused port definition genpc_stop_prefetch and some synthesis tools had problems with unsused ports. It is no longer there so don't worry about it. [q]> I measured the jtag module signals with an oscilloscope and [/q] sometimes the clk [q]> signal isn't go to the 3,3V peak just approximateli 1,7V is it [/q] a normal or my jtag [q]> module isn't work properly? [/q] It is rather low. Check your datasheet for the FPGA what is the lowest VIH level for clock input. BTW make sure your clock inputs of SOC are using clock inputs of FPGA. regards, Damjan [q]> > Thank you your anwser! > > Best regards > Erno Varga > > > > ----- Original Message ----- > From: Damjan Lampret<<A HREF="mailto:damjanl@o...">damjanl@o...</A>> > To: > Date: Fri Jul 23 17:35:31 CEST 2004 > Subject: [openrisc] jp1 server > [q]> > If I use just some modules (or1k,debug unit, uart, [/q] cop matrix) [q] > the jp1 > server could [q]> > communicate the Soc? [/q] > Yes or1k and debug are enough to connect jp1 / gdb. > There are two versions of debug, one that works with jp1 [/q] and one [q] > that works > with jp2. Make sure you use the right one. The tutorial [/q] is for jp1 [q] > (but the > concept is the same for jp2) > [/q] <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf">http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf</A> [q] > [/q] <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf">http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf</A> [q] > regards, > Damjan > > [/q] > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > [/q] [/q] Dear Damjan, Thank you your help, the jp1 server works, there was a problem with the jtag negated reset and the jtag module. The next step is the hello word implementation, I checked and correct the hello.c, board.h, and ram.ld like the SW tutorial. board.h and ram.ld there are some differences because on my SoC there are IC and DC and the onchip ram is smaller (2k) than the example. I make the hello.or32 and start the gdb, but when I write the following instruction:target jtag jtag://localhost:9999 I get an error message: Unable to set flags for JTAG proxy socket 5 to value 0x401d79c0 I don't know what cause these problem, I think it's free from the hello word c files, maybe the gdb installation is wrong but I followed the toolchain instructins (I use Mandrake Linux)? I have to start the jp1 server before run the gdb or not? Thank yuo your kindness! Best regards! Erno Varga ----- Original Message ----- From: Damjan Lampretdamjanl@o...> To: Date: Tue Jul 27 04:22:54 CEST 2004 Subject: [openrisc] jp1 server ----- Original Message ----- From: verno@a...> To: openrisc@o...> Sent: Monday, July 26, 2004 6:09 PM Subject: Re: [openrisc] jp1 server > Dear Damjan, > Thank you your quick anwser. I have read the hardware and software tutorial and > followed the directions, but unfortunately the jp1 server couldn't communicate with > the SoC. I read the the jp1.c file and found that in xilinx mode it isn't use the > trst_pad_i, but on the dbg_top.v there is a trst signal. I put the trst signal to switch > which is on the board and before I use the jp1 software push the reset button is it > good method or not? Yes it should be OK. > The ISE write: the application could work up to 50MHz, so I just put the clk signal > to the MEMEC board 24MHz signal. The WISHBONE_clk and the clk is the same > in my SoC. I'm not use the ibufg modul (if I use the ISE write an error ngdbuild > 466 ) and not use the CLKDLL. > On the HW tutorial there is an instruction remove .genpc_stop_prefetch > (genpc_stop_prefetch) the line from the or1200_cpu.v, the newest ORP there isn't > a line like this .genpc_stop_prefetch (1'b0) is it good or I have to remove it? You can ignore this. There used to be unused port definition genpc_stop_prefetch and some synthesis tools had problems with unsused ports. It is no longer there so don't worry about it. > I measured the jtag module signals with an oscilloscope and sometimes the clk > signal isn't go to the 3,3V peak just approximateli 1,7V is it a normal or my jtag > module isn't work properly? It is rather low. Check your datasheet for the FPGA what is the lowest VIH level for clock input. BTW make sure your clock inputs of SOC are using clock inputs of FPGA. regards, Damjan > > Thank you your anwser! > > Best regards > Erno Varga > > > > ----- Original Message ----- > From: Damjan Lampretdamjanl@o...> > To: > Date: Fri Jul 23 17:35:31 CEST 2004 > Subject: [openrisc] jp1 server > > > If I use just some modules (or1k,debug unit, uart, cop matrix) > the jp1 > server could > > communicate the Soc? > Yes or1k and debug are enough to connect jp1 / gdb. > There are two versions of debug, one that works with jp1 and one > that works > with jp2. Make sure you use the right one. The tutorial is for jp1 > (but the > concept is the same for jp2) > http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf > http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf > regards, > Damjan > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc >

jp1 server by Unknown on Jul 30, 2004			Not available!
Erno yes you have to start jp1 before starting gdb. jp1 is a kind of proxy/driver to generate JTAG on parallel port. So it has to be started before gdb so that gdb can to talk to the board through jp1. regards, Damjan ----- Original Message ----- From: <<A HREF="mailto:verno@analogic-computers.com">verno@analogic-computers.com</A>> To: <<A HREF="mailto:openrisc@opencores.org">openrisc@opencores.org</A>> Sent: Friday, July 30, 2004 8:42 AM Subject: Re: [openrisc] jp1 server [q] Dear Damjan, Thank you your help, the jp1 server works, there was a problem with the jtag negated reset and the jtag module. The next step is the hello word implementation, I checked and correct the hello.c, board.h, and ram.ld like the SW tutorial. board.h and ram.ld there are some differences because on my SoC there are IC and DC and the onchip ram is smaller (2k) than the example. I make the hello.or32 and start the gdb, but when I write the following instruction:target jtag <A HREF="jtag://localhost:9999">jtag://localhost:9999</A> I get an error message: Unable to set flags for JTAG proxy socket 5 to value 0x401d79c0 I don't know what cause these problem, I think it's free from the hello word c files, maybe the gdb installation is wrong but[/q] I [q] followed the toolchain instructins (I use Mandrake Linux)? I have to start the jp1 server before run the gdb or not? Thank yuo your kindness! Best regards! Erno Varga ----- Original Message ----- From: Damjan Lampret<<A HREF="mailto:damjanl@o...">damjanl@o...</A>> To: Date: Tue Jul 27 04:22:54 CEST 2004 Subject: [openrisc] jp1 server [q]> ----- Original Message ----- > From: <<A HREF="mailto:verno@a...">verno@a...</A>> > To: <<A HREF="mailto:openrisc@o...">openrisc@o...</A>> > Sent: Monday, July 26, 2004 6:09 PM > Subject: Re: [openrisc] jp1 server [q] > Dear Damjan, > Thank you your quick anwser. I have read the hardware and[/q] > software > tutorial and [q] > followed the directions, but unfortunately the jp1 server[/q] > couldn't > communicate with [q] > the SoC. I read the the jp1.c file and found that in xilinx[/q] > mode it isn't > use the [q] > trst_pad_i, but on the dbg_top.v there is a trst signal. I put[/q] > the trst > signal to switch [q] > which is on the board and before I use the jp1 software push[/q] > the reset > button is it [q] > good method or not?[/q] > Yes it should be OK. [q] > The ISE write: the application could work up to 50MHz, so I[/q] > just put the > clk signal [q] > to the MEMEC board 24MHz signal. The WISHBONE_clk and the clk[/q] > is the same [q] > in my SoC. I'm not use the ibufg modul (if I use the ISE write[/q] > an error > ngdbuild [q] > 466 ) and not use the CLKDLL. > On the HW tutorial there is an instruction remove[/q] > .genpc_stop_prefetch [q] > (genpc_stop_prefetch) the line from the or1200_cpu.v, the[/q] > newest ORP there > isn't [q] > a line like this .genpc_stop_prefetch (1'b0) is it good or I[/q] > have to > remove it? > You can ignore this. There used to be unused port definition > genpc_stop_prefetch and some synthesis tools had problems with > unsused > ports. It is no longer there so don't worry about it. [q] > I measured the jtag module signals with an oscilloscope and[/q] > sometimes the > clk [q] > signal isn't go to the 3,3V peak just approximateli 1,7V is it[/q] > a normal or > my jtag [q] > module isn't work properly?[/q] > It is rather low. Check your datasheet for the FPGA what is the > lowest VIH > level for clock input. BTW make sure your clock inputs of SOC are > using > clock inputs of FPGA. > regards, > Damjan [q] > > Thank you your anwser! > > Best regards > Erno Varga > > > > ----- Original Message ----- > From: Damjan Lampret<<A HREF="mailto:damjanl@o...">damjanl@o...</A>> > To: > Date: Fri Jul 23 17:35:31 CEST 2004 > Subject: [openrisc] jp1 server > [q] > > If I use just some modules (or1k,debug unit, uart,[/q] > cop matrix) [q]> > the jp1 > > server could [q] > > communicate the Soc?[/q] > > Yes or1k and debug are enough to connect jp1 / gdb. > > There are two versions of debug, one that works with jp1[/q] > and one [q]> > that works > > with jp2. Make sure you use the right one. The tutorial[/q] > is for jp1 [q]> > (but the > > concept is the same for jp2) > >[/q] > <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf">http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf</A> [q]> >[/q] > <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf">http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf</A> [q]> > regards, > > Damjan > > > >[/q] > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> >[/q] > >[/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A>[/q] Erno yes you have to start jp1 before starting gdb. jp1 is a kind of proxy/driver to generate JTAG on parallel port. So it has to be started before gdb so that gdb can to talk to the board through jp1. regards, Damjan ----- Original Message ----- From: verno@analogic-computers.com> To: openrisc@opencores.org> Sent: Friday, July 30, 2004 8:42 AM Subject: Re: [openrisc] jp1 server Dear Damjan, Thank you your help, the jp1 server works, there was a problem with the jtag negated reset and the jtag module. The next step is the hello word implementation, I checked and correct the hello.c, board.h, and ram.ld like the SW tutorial. board.h and ram.ld there are some differences because on my SoC there are IC and DC and the onchip ram is smaller (2k) than the example. I make the hello.or32 and start the gdb, but when I write the following instruction:target jtag jtag://localhost:9999 I get an error message: Unable to set flags for JTAG proxy socket 5 to value 0x401d79c0 I don't know what cause these problem, I think it's free from the hello word c files, maybe the gdb installation is wrong but I followed the toolchain instructins (I use Mandrake Linux)? I have to start the jp1 server before run the gdb or not? Thank yuo your kindness! Best regards! Erno Varga ----- Original Message ----- From: Damjan Lampretdamjanl@o...> To: Date: Tue Jul 27 04:22:54 CEST 2004 Subject: [openrisc] jp1 server > ----- Original Message ----- > From: verno@a...> > To: openrisc@o...> > Sent: Monday, July 26, 2004 6:09 PM > Subject: Re: [openrisc] jp1 server > Dear Damjan, > Thank you your quick anwser. I have read the hardware and > software > tutorial and > followed the directions, but unfortunately the jp1 server > couldn't > communicate with > the SoC. I read the the jp1.c file and found that in xilinx > mode it isn't > use the > trst_pad_i, but on the dbg_top.v there is a trst signal. I put > the trst > signal to switch > which is on the board and before I use the jp1 software push > the reset > button is it > good method or not? > Yes it should be OK. > The ISE write: the application could work up to 50MHz, so I > just put the > clk signal > to the MEMEC board 24MHz signal. The WISHBONE_clk and the clk > is the same > in my SoC. I'm not use the ibufg modul (if I use the ISE write > an error > ngdbuild > 466 ) and not use the CLKDLL. > On the HW tutorial there is an instruction remove > .genpc_stop_prefetch > (genpc_stop_prefetch) the line from the or1200_cpu.v, the > newest ORP there > isn't > a line like this .genpc_stop_prefetch (1'b0) is it good or I > have to > remove it? > You can ignore this. There used to be unused port definition > genpc_stop_prefetch and some synthesis tools had problems with > unsused > ports. It is no longer there so don't worry about it. > I measured the jtag module signals with an oscilloscope and > sometimes the > clk > signal isn't go to the 3,3V peak just approximateli 1,7V is it > a normal or > my jtag > module isn't work properly? > It is rather low. Check your datasheet for the FPGA what is the > lowest VIH > level for clock input. BTW make sure your clock inputs of SOC are > using > clock inputs of FPGA. > regards, > Damjan > > Thank you your anwser! > > Best regards > Erno Varga > > > > ----- Original Message ----- > From: Damjan Lampretdamjanl@o...> > To: > Date: Fri Jul 23 17:35:31 CEST 2004 > Subject: [openrisc] jp1 server > > > If I use just some modules (or1k,debug unit, uart, > cop matrix) > > the jp1 > > server could > > communicate the Soc? > > Yes or1k and debug are enough to connect jp1 / gdb. > > There are two versions of debug, one that works with jp1 > and one > > that works > > with jp2. Make sure you use the right one. The tutorial > is for jp1 > > (but the > > concept is the same for jp2) > > > http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf > > > http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf > > regards, > > Damjan > > > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > > > _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

jp1 server by Unknown on Oct 18, 2004			Not available!
Hi! We have the exact same problem when trying to run the jtag and gdb software. We start jp1 (./jp1-xilinx 9999) and get the correct readback, as shown in the SW tutorial. When trying to run gdb with the hello world-program we get this output from the jtag software (after typing "target jtag <A HREF="jtag://localhost:9999"">jtag://localhost:9999"</A> in gdb): "Unable to set flags for gdb socket 4 to value 0x40017d78 (1): Invalid argument" and this from the gdb tool: "An error was reported by the proxy server. The command was: "JTAG_COMMAND_CHAIN",1. The command returned 104." We are also using Mandrake Linux. ----- Original Message ----- From: Damjan Lampret<<A HREF="mailto:damjanl@o...">damjanl@o...</A>> To: Date: Fri Jul 30 08:42:55 CEST 2004 Subject: [openrisc] jp1 server [q] Erno yes you have to start jp1 before starting gdb. jp1 is a kind of proxy/driver to generate JTAG on parallel port. So it has to be started before gdb so that gdb can to talk to the board through jp1. regards, Damjan ----- Original Message ----- From: <<A HREF="mailto:verno@a...">verno@a...</A>> To: <<A HREF="mailto:openrisc@o...">openrisc@o...</A>> Sent: Friday, July 30, 2004 8:42 AM Subject: Re: [openrisc] jp1 server [q]> Dear Damjan, > Thank you your help, the jp1 server works, there was a problem [/q] with the [q]> jtag negated reset and the jtag module. The next step is the [/q] hello word [q]> implementation, I checked and correct the hello.c, board.h, [/q] and ram.ld [q]> like the SW tutorial. board.h and ram.ld there are some [/q] differences [q]> because on my SoC there are IC and DC and the onchip ram is [/q] smaller [q]> (2k) than the example. I make the hello.or32 and start the [/q] gdb, but [q]> when I write the following instruction:target jtag [/q] <A HREF="jtag://localhost:9999">jtag://localhost:9999</A> [q]> I get an error message: Unable to set flags for JTAG proxy [/q] socket 5 to [q]> value 0x401d79c0 I don't know what cause these problem, I [/q] think it's [q]> free from the hello word c files, maybe the gdb installation [/q] is wrong but I [q]> followed the toolchain instructins (I use Mandrake Linux)? > > I have to start the jp1 server before run the gdb or not? > > Thank yuo your kindness! > Best regards! > Erno Varga > > ----- Original Message ----- > From: Damjan Lampret<<A HREF="mailto:damjanl@o...">damjanl@o...</A>> > To: > Date: Tue Jul 27 04:22:54 CEST 2004 > Subject: [openrisc] jp1 server > [q] > ----- Original Message ----- > From: <<A HREF="mailto:verno@a...">verno@a...</A>> > To: <<A HREF="mailto:openrisc@o...">openrisc@o...</A>> > Sent: Monday, July 26, 2004 6:09 PM > Subject: Re: [openrisc] jp1 server [q]> > Dear Damjan, > > Thank you your quick anwser. I have read the [/q] hardware and [q] > software > tutorial and [q]> > followed the directions, but unfortunately the jp1 [/q] server [q] > couldn't > communicate with [q]> > the SoC. I read the the jp1.c file and found that in [/q] xilinx [q] > mode it isn't > use the [q]> > trst_pad_i, but on the dbg_top.v there is a trst [/q] signal. I put [q] > the trst > signal to switch [q]> > which is on the board and before I use the jp1 [/q] software push [q] > the reset > button is it [q]> > good method or not? [/q] > Yes it should be OK. [q]> > The ISE write: the application could work up to [/q] 50MHz, so I [q] > just put the > clk signal [q]> > to the MEMEC board 24MHz signal. The WISHBONE_clk [/q] and the clk [q] > is the same [q]> > in my SoC. I'm not use the ibufg modul (if I use the [/q] ISE write [q] > an error > ngdbuild [q]> > 466 ) and not use the CLKDLL. > > On the HW tutorial there is an instruction remove [/q] > .genpc_stop_prefetch [q]> > (genpc_stop_prefetch) the line from the [/q] or1200_cpu.v, the [q] > newest ORP there > isn't [q]> > a line like this .genpc_stop_prefetch (1'b0) is it [/q] good or I [q] > have to > remove it? > You can ignore this. There used to be unused port [/q] definition [q] > genpc_stop_prefetch and some synthesis tools had problems [/q] with [q] > unsused > ports. It is no longer there so don't worry about it. [q]> > I measured the jtag module signals with an [/q] oscilloscope and [q] > sometimes the > clk [q]> > signal isn't go to the 3,3V peak just approximateli [/q] 1,7V is it [q] > a normal or > my jtag [q]> > module isn't work properly? [/q] > It is rather low. Check your datasheet for the FPGA what [/q] is the [q] > lowest VIH > level for clock input. BTW make sure your clock inputs of [/q] SOC are [q] > using > clock inputs of FPGA. > regards, > Damjan [q]> > > > Thank you your anwser! [q] > > > Best regards > > > Erno [/q] Varga > > > > > > > > > > > > ----- Original Message ----- > > > From: Damjan Lampret<<A HREF="mailto:damjanl@o...">damjanl@o...</A>> > > > To: > > > Date: Fri Jul 23 17:35:31 CEST 2004 > > > Subject: [openrisc] jp1 server > > > > > > > > If I use just some modules (or1k,debug unit, uart, > > cop matrix) > [q]> > the jp1 > > > > server could > > > > communicate the Soc? > > > > Yes or1k [/q] and debug are enough to connect jp1 / gdb. > > > > There are two versions of debug, one that works with jp1 > > and one > > > > that works > > > > with jp2. Make sure you use the right one. The tutorial > > is for jp1 > > > > (but the > > > > concept is the same for jp2) > > > > > > <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf">http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf</A> > [q]> > > [/q] <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf">http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf</A> [q] > > regards, > > > > Damjan > > [q]> > > > > [/q] _______________________________________________ > > > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > > > [q]> > > [/q] _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> [/q] Hi! We have the exact same problem when trying to run the jtag and gdb software. We start jp1 (./jp1-xilinx 9999) and get the correct readback, as shown in the SW tutorial. When trying to run gdb with the hello world-program we get this output from the jtag software (after typing "target jtag jtag://localhost:9999" in gdb): "Unable to set flags for gdb socket 4 to value 0x40017d78 (1): Invalid argument" and this from the gdb tool: "An error was reported by the proxy server. The command was: "JTAG_COMMAND_CHAIN",1. The command returned 104." We are also using Mandrake Linux. ----- Original Message ----- From: Damjan Lampretdamjanl@o...> To: Date: Fri Jul 30 08:42:55 CEST 2004 Subject: [openrisc] jp1 server Erno yes you have to start jp1 before starting gdb. jp1 is a kind of proxy/driver to generate JTAG on parallel port. So it has to be started before gdb so that gdb can to talk to the board through jp1. regards, Damjan ----- Original Message ----- From: verno@a...> To: openrisc@o...> Sent: Friday, July 30, 2004 8:42 AM Subject: Re: [openrisc] jp1 server > Dear Damjan, > Thank you your help, the jp1 server works, there was a problem with the > jtag negated reset and the jtag module. The next step is the hello word > implementation, I checked and correct the hello.c, board.h, and ram.ld > like the SW tutorial. board.h and ram.ld there are some differences > because on my SoC there are IC and DC and the onchip ram is smaller > (2k) than the example. I make the hello.or32 and start the gdb, but > when I write the following instruction:target jtag jtag://localhost:9999 > I get an error message: Unable to set flags for JTAG proxy socket 5 to > value 0x401d79c0 I don't know what cause these problem, I think it's > free from the hello word c files, maybe the gdb installation is wrong but I > followed the toolchain instructins (I use Mandrake Linux)? > > I have to start the jp1 server before run the gdb or not? > > Thank yuo your kindness! > Best regards! > Erno Varga > > ----- Original Message ----- > From: Damjan Lampretdamjanl@o...> > To: > Date: Tue Jul 27 04:22:54 CEST 2004 > Subject: [openrisc] jp1 server > > ----- Original Message ----- > From: verno@a...> > To: openrisc@o...> > Sent: Monday, July 26, 2004 6:09 PM > Subject: Re: [openrisc] jp1 server > > Dear Damjan, > > Thank you your quick anwser. I have read the hardware and > software > tutorial and > > followed the directions, but unfortunately the jp1 server > couldn't > communicate with > > the SoC. I read the the jp1.c file and found that in xilinx > mode it isn't > use the > > trst_pad_i, but on the dbg_top.v there is a trst signal. I put > the trst > signal to switch > > which is on the board and before I use the jp1 software push > the reset > button is it > > good method or not? > Yes it should be OK. > > The ISE write: the application could work up to 50MHz, so I > just put the > clk signal > > to the MEMEC board 24MHz signal. The WISHBONE_clk and the clk > is the same > > in my SoC. I'm not use the ibufg modul (if I use the ISE write > an error > ngdbuild > > 466 ) and not use the CLKDLL. > > On the HW tutorial there is an instruction remove > .genpc_stop_prefetch > > (genpc_stop_prefetch) the line from the or1200_cpu.v, the > newest ORP there > isn't > > a line like this .genpc_stop_prefetch (1'b0) is it good or I > have to > remove it? > You can ignore this. There used to be unused port definition > genpc_stop_prefetch and some synthesis tools had problems with > unsused > ports. It is no longer there so don't worry about it. > > I measured the jtag module signals with an oscilloscope and > sometimes the > clk > > signal isn't go to the 3,3V peak just approximateli 1,7V is it > a normal or > my jtag > > module isn't work properly? > It is rather low. Check your datasheet for the FPGA what is the > lowest VIH > level for clock input. BTW make sure your clock inputs of SOC are > using > clock inputs of FPGA. > regards, > Damjan > > > > Thank you your anwser! > > > Best regards > > > Erno Varga > > > > > > > > > > > > ----- Original Message ----- > > > From: Damjan Lampretdamjanl@o...> > > > To: > > > Date: Fri Jul 23 17:35:31 CEST 2004 > > > Subject: [openrisc] jp1 server > > > > > > > > If I use just some modules (or1k,debug unit, uart, > > cop matrix) > > > the jp1 > > > > server could > > > > communicate the Soc? > > > > Yes or1k and debug are enough to connect jp1 / gdb. > > > > There are two versions of debug, one that works with jp1 > > and one > > > > that works > > > > with jp2. Make sure you use the right one. The tutorial > > is for jp1 > > > > (but the > > > > concept is the same for jp2) > > > > > > http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf > > > > http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf > > regards, > > > > Damjan > > > > > > > _______________________________________________ > > > http://www.opencores.org/mailman/listinfo/openrisc > > > > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc

jp1 server by Unknown on Dec 2, 2004			Not available!
Hi Erno, I have run into a similar problem as you. The Jtag interface (JP1) does not work for me. Can you please let me know in detail , which of the reset you used and what jtag module you fixed. Thanks, Farhan ----- Original Message ----- From: <A HREF="mailto:verno@a...">verno@a...</A><<A HREF="mailto:verno@a...">verno@a...</A>> To: Date: Fri Jul 30 08:42:19 CEST 2004 Subject: [openrisc] jp1 server [q] Dear Damjan, Thank you your help, the jp1 server works, there was a problem with the jtag negated reset and the jtag module. The next step is the hello word implementation, I checked and correct the hello.c, board.h, and ram.ld like the SW tutorial. board.h and ram.ld there are some differences because on my SoC there are IC and DC and the onchip ram is smaller (2k) than the example. I make the hello.or32 and start the gdb, but when I write the following instruction:target jtag <A HREF="jtag://localhost:9999">jtag://localhost:9999</A> I get an error message: Unable to set flags for JTAG proxy socket 5 to value 0x401d79c0 I don't know what cause these problem, I think it's free from the hello word c files, maybe the gdb installation is wrong but I followed the toolchain instructins (I use Mandrake Linux)? I have to start the jp1 server before run the gdb or not? Thank yuo your kindness! Best regards! Erno Varga ----- Original Message ----- From: Damjan Lampret<<A HREF="mailto:damjanl@o...">damjanl@o...</A>> To: Date: Tue Jul 27 04:22:54 CEST 2004 Subject: [openrisc] jp1 server [q]> ----- Original Message ----- > From: <<A HREF="mailto:verno@a...">verno@a...</A>> > To: <<A HREF="mailto:openrisc@o...">openrisc@o...</A>> > Sent: Monday, July 26, 2004 6:09 PM > Subject: Re: [openrisc] jp1 server [q] > Dear Damjan, > Thank you your quick anwser. I have read the hardware and [/q] > software > tutorial and [q] > followed the directions, but unfortunately the jp1 server [/q] > couldn't > communicate with [q] > the SoC. I read the the jp1.c file and found that in [/q] xilinx [q]> mode it isn't > use the [q] > trst_pad_i, but on the dbg_top.v there is a trst signal. [/q] I put [q]> the trst > signal to switch [q] > which is on the board and before I use the jp1 software [/q] push [q]> the reset > button is it [q] > good method or not? [/q] > Yes it should be OK. [q] > The ISE write: the application could work up to 50MHz, so [/q] I [q]> just put the > clk signal [q] > to the MEMEC board 24MHz signal. The WISHBONE_clk and the [/q] clk [q]> is the same [q] > in my SoC. I'm not use the ibufg modul (if I use the ISE [/q] write [q]> an error > ngdbuild [q] > 466 ) and not use the CLKDLL. > On the HW tutorial there is an instruction remove [/q] > .genpc_stop_prefetch [q] > (genpc_stop_prefetch) the line from the or1200_cpu.v, the [/q] > newest ORP there > isn't [q] > a line like this .genpc_stop_prefetch (1'b0) is it good [/q] or I [q]> have to > remove it? > You can ignore this. There used to be unused port definition > genpc_stop_prefetch and some synthesis tools had problems with > unsused > ports. It is no longer there so don't worry about it. [q] > I measured the jtag module signals with an oscilloscope [/q] and [q]> sometimes the > clk [q] > signal isn't go to the 3,3V peak just approximateli 1,7V [/q] is it [q]> a normal or > my jtag [q] > module isn't work properly? [/q] > It is rather low. Check your datasheet for the FPGA what is [/q] the [q]> lowest VIH > level for clock input. BTW make sure your clock inputs of SOC [/q] are [q]> using > clock inputs of FPGA. > regards, > Damjan [q] > > Thank you your anwser! > > Best regards > Erno Varga > > > > ----- Original Message ----- > From: Damjan Lampret<<A HREF="mailto:damjanl@o...">damjanl@o...</A>> > To: > Date: Fri Jul 23 17:35:31 CEST 2004 > Subject: [openrisc] jp1 server > [q] > > If I use just some modules (or1k,debug unit, [/q] uart, [q]> cop matrix) [q]> > the jp1 > > server could > > > > communicate the [/q] Soc? > > > Yes or1k and debug are enough to connect jp1 / gdb. > > > There are two versions of debug, one that works with jp1 > and one > > > that works > > > with jp2. Make sure you use the right one. The tutorial > is for jp1 [q]> > (but the > > > concept is the same for jp2) [q] > > [/q] <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf">http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf</A> > [q]> > [/q] <A HREF="http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf">http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf</A> [q]> > regards, > > > Damjan > > > > [q] > > _______________________________________________ [/q] > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > [q]> > [/q] [/q] Hi Erno, I have run into a similar problem as you. The Jtag interface (JP1) does not work for me. Can you please let me know in detail , which of the reset you used and what jtag module you fixed. Thanks, Farhan ----- Original Message ----- From: verno@a...verno@a...> To: Date: Fri Jul 30 08:42:19 CEST 2004 Subject: [openrisc] jp1 server Dear Damjan, Thank you your help, the jp1 server works, there was a problem with the jtag negated reset and the jtag module. The next step is the hello word implementation, I checked and correct the hello.c, board.h, and ram.ld like the SW tutorial. board.h and ram.ld there are some differences because on my SoC there are IC and DC and the onchip ram is smaller (2k) than the example. I make the hello.or32 and start the gdb, but when I write the following instruction:target jtag jtag://localhost:9999 I get an error message: Unable to set flags for JTAG proxy socket 5 to value 0x401d79c0 I don't know what cause these problem, I think it's free from the hello word c files, maybe the gdb installation is wrong but I followed the toolchain instructins (I use Mandrake Linux)? I have to start the jp1 server before run the gdb or not? Thank yuo your kindness! Best regards! Erno Varga ----- Original Message ----- From: Damjan Lampretdamjanl@o...> To: Date: Tue Jul 27 04:22:54 CEST 2004 Subject: [openrisc] jp1 server > ----- Original Message ----- > From: verno@a...> > To: openrisc@o...> > Sent: Monday, July 26, 2004 6:09 PM > Subject: Re: [openrisc] jp1 server > Dear Damjan, > Thank you your quick anwser. I have read the hardware and > software > tutorial and > followed the directions, but unfortunately the jp1 server > couldn't > communicate with > the SoC. I read the the jp1.c file and found that in xilinx > mode it isn't > use the > trst_pad_i, but on the dbg_top.v there is a trst signal. I put > the trst > signal to switch > which is on the board and before I use the jp1 software push > the reset > button is it > good method or not? > Yes it should be OK. > The ISE write: the application could work up to 50MHz, so I > just put the > clk signal > to the MEMEC board 24MHz signal. The WISHBONE_clk and the clk > is the same > in my SoC. I'm not use the ibufg modul (if I use the ISE write > an error > ngdbuild > 466 ) and not use the CLKDLL. > On the HW tutorial there is an instruction remove > .genpc_stop_prefetch > (genpc_stop_prefetch) the line from the or1200_cpu.v, the > newest ORP there > isn't > a line like this .genpc_stop_prefetch (1'b0) is it good or I > have to > remove it? > You can ignore this. There used to be unused port definition > genpc_stop_prefetch and some synthesis tools had problems with > unsused > ports. It is no longer there so don't worry about it. > I measured the jtag module signals with an oscilloscope and > sometimes the > clk > signal isn't go to the 3,3V peak just approximateli 1,7V is it > a normal or > my jtag > module isn't work properly? > It is rather low. Check your datasheet for the FPGA what is the > lowest VIH > level for clock input. BTW make sure your clock inputs of SOC are > using > clock inputs of FPGA. > regards, > Damjan > > Thank you your anwser! > > Best regards > Erno Varga > > > > ----- Original Message ----- > From: Damjan Lampretdamjanl@o...> > To: > Date: Fri Jul 23 17:35:31 CEST 2004 > Subject: [openrisc] jp1 server > > > If I use just some modules (or1k,debug unit, uart, > cop matrix) > > the jp1 > > server could > > > > communicate the Soc? > > > Yes or1k and debug are enough to connect jp1 / gdb. > > > There are two versions of debug, one that works with jp1 > and one > > > that works > > > with jp2. Make sure you use the right one. The tutorial > is for jp1 > > (but the > > > concept is the same for jp2) > > http://emsys.denayer.wenk.be/empro/openrisc-SW-tutorial.pdf > > > http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf > > regards, > > > Damjan > > > > > > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > > >

no use

no use

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