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Bug in nc.scr file in orp/orp_soc
by JavierCastillo on Jul 27, 2004 |
JavierCastillo
Posts: 9 Joined: Oct 29, 2018 Last seen: Jul 11, 2026 |
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Hello:
I found a little bug in orp_soc simulation scripts. To simulate OpenRisc platform with ncverilog you have to add in file nc.src file the following line in the uart16550 sources section: ../../rtl/verilog/uart16550/uart_sync_flops.v Regards Javier Castillo |
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