* Dysthymicdolt@aol.com (Dysthymicdolt@aol.com) wrote:

only 8 Kb pages are implemented right now.
we had discussions about usefulness of ~16 Mb page support but didn't come
to any other conclusion then there other features we would benefit more
from right now.

you can find out more about huge page ('area translation') support in the
architectual manual. the discussion is welcomed if anyone has any
suggestions.

best regards,
p.

Are there any plans to support large (e.g., 32KiB) pages? One possible implementation framework would be to have each TLB way have two banks and have the large-page seek invert one of the bits of virtual address (guaranteeing that each look-up would go to a different bank) and have the large-page seek replace the two least signficiant bits of the regular page index with the two bits more significant than those used in the regular page indexing. In this way most of the row decode could be shared if desired, and (more importantly) all of the TLB is available for both sizes of pages. (BTW, are OR1200's TLBs indices decoded in big-endian order? This would seem have the potential to save a slight amount of power because the MSbs tend to change less frequently. Unfortunately, I have not learned verilog, so I cannot check this for myself.) Paul A. Clayton just a technophile -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/openrisc/attachments/20040918/327e22ae/attachment-0001.htm

pheonix@opencores.org wrote:

Agreed (though I would like to see ATBs with directory entry support).


I have already read through it (twice if one counts a pre-1 version :-).
While huge pages have some uses, large pages can be more generally
useful. A 32KiB page would not even require special PTE support--the
TLB fill method could look at all four PTEs and use a large page entry
in the TLB if appropriate. Some architectures support several page
sizes in 4x intervals. The main benefit is reducing TLB misses.

(TLB entries can also be extended such that a single virtual address
tag is applied for two adjacent pages with two different physical
address values provided [and two valid bits]. For a small fully-
associative TLB, this has some advantages.)

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