Have supervisor-allocating caches been considered? For an instruction cache, such would be something like certain ARMs' instruction minicaches, allowing some interrupt code to remain resident and not to interfere with application code. In supervisor mode the regular Icache could be ignored (and put into a power-saving mode); in user mode, the supervisor cache could be ignored (and similarly placed in a power-saving mode). For a supervisor data cache, allocations could be limited to the supervisor cache, but the user Dcache would have to be snooped on write misses (and should probably be snooped on read misses [this could be done in parallel or partially in parallel {e.g., only checking the tags of the less likely partition, allowing the data portion to remain in a power-saving mode}])--in user mode, the supervisor Dcache would likewise need to be snooped. For an Icache, this would seem likely to provide a modest benefit for minimal added complexity. For a Dcache, the benefit/complexity tradeoff is less clear. Paul A. Clayton -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/openrisc/attachments/20041005/4fe1b96e/attachment.htm