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RTL Simulation using Modelsim
by Unknown on Oct 8, 2004 |
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Hi
Has anyone managed to get a simulation running successfully using Modelsim? I have the ORP_SOC system running in simulation fine (as in no errors) but the flash.in file I'm using doesn't seem to be running as it should - the waveforms for the CPU are not changing as they should, it appears as if the system is idle. The flash.in file I'm using is a uClinux with a basic application to write some output. Using the software simulator this runs fine, and I can send shell commands such as "ls" to the shell using the simulated UART and view the output. On my RTL simulation I have the UART output redirected to a text file, I don't expect any output here until simulation has been running for some time but of couse the CPU has to be switching otherwise it's not doing anything. One other thing - what top level file are people using for RTL simulation? The "testbench_top.v" file is obviously not the top level as it has a clock input rather than generating a clock. So I have a file called "main_top.v" modified slightly but I can't remember where it came from! Thanks Paul. |
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RTL Simulation using Modelsim
by Unknown on Oct 8, 2004 |
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anybody really simulated the whole system in RTL?!
I would think it is too slow unless you have a Milkway-4.
---Botao
At 09:25 AM 10/8/2004, paul_morga@yahoo.co.uk wrote:
Hi
Has anyone managed to get a simulation running successfully using
Modelsim? I have the ORP_SOC system running in simulation fine (as in
no errors) but the flash.in file I'm using doesn't seem to be running
as it should - the waveforms for the CPU are not changing as they
should, it appears as if the system is idle.
The flash.in file I'm using is a uClinux with a basic application to
write some output. Using the software simulator this runs fine, and I
can send shell commands such as "ls" to the shell using the simulated
UART and view the output. On my RTL simulation I have the UART output
redirected to a text file, I don't expect any output here until
simulation has been running for some time but of couse the CPU has to
be switching otherwise it's not doing anything.
One other thing - what top level file are people using for RTL
simulation? The "testbench_top.v" file is obviously not the top level
as it has a clock input rather than generating a clock. So I have a
file called "main_top.v" modified slightly but I can't remember where
it came from!
Thanks
Paul.
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RTL Simulation using Modelsim
by Unknown on Oct 11, 2004 |
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----- Original Message -----
From: Botao Leeblee@q...>
To:
Date: Fri Oct 8 18:45:58 CEST 2004
Subject: [openrisc] RTL Simulation using Modelsim
anybody really simulated the whole system in RTL?!
I would think it is too slow unless you have a Milkway-4. ---Botao I expect it will be rather slow, but I would only be interested in running to get some switching activity for power analysis rather than development. So it would need to be run only once (assuming only one software application being simulated on the core). It has been done by others on this forum, so there's no reason why it shouldn't be possible in Modelsim. Paul. |
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