greetings everybody!

since cvs checkins list still doesn't work i'd like to let you know i've
just checked in a major bugfix package to or1ksim. these include:

- strict memory access statistics (separated the
accesses cpu would do and the one needed only in simulator). the
cycles count should be much more reliable now (i went through all
read/write functions and fixed the type if neccessery but there may be
some mistakes). the result is hopefully correct but even
uglier abstract.[ch], so this is probably just a first step in some sort
of rewrite/cleanup at some later time...

- made sure that having enabled 'execution log' doesn't affect tlb
miss exceptions, cycle statistics,... (i hope i caught and fixed all cases that
caused such differences)

- fix for a rare (but nasty) or1ksim bug that happened when tick timer
exception went of at exactly the instruction that caused dtlb miss.

- fix for a freeze after 0x7fffffff
of sim.cycles. (with a resonable memory timings in sim.cfg this occured in
few minutes on high end machine).

- fix for the problem Adrian Wise reported (i've ended bumping
up MAX_OPERANDS - it looks like the RightThingToDo(tm)). Adrian, could
you please let me know if it fixes the problem on Solaris.

i've haven't seen any problems with this package of changes.
nevertheless i wellcome any corrections, bug/breakage reports...

best regards,
p.