Hello,

I would like to know if either the Openrisc 1000 or 1200 is SuperScalar.

Thanks in advance.

Bruno

Hi, Who can tell me what's the meaning of "super scalar"? Sorry! I'm a newer with FPGA. Thanks first! Zhong_cx ----- Original Message ----- From: "Bruno De Maesschalck" bdm@mgb-tech.com> To: openrisc@opencores.org>; bdm@mgb-tech.com> Sent: Monday, November 01, 2004 9:51 PM Subject: [openrisc] Super Scalar

No. regards, Damjan ----- Original Message ----- From: "Bruno De Maesschalck" bdm@mgb-tech.com> To: openrisc@opencores.org>; bdm@mgb-tech.com> Sent: Monday, November 01, 2004 2:51 PM Subject: [openrisc] Super Scalar

Zhong, Try this A superscalar CPU architecture implements a form of parallelism on a single chip, thereby allowing the system as a whole to run much faster than it would otherwise be able to at a given clock speed. The term is a modification of scalar, processors that run one instruction per clock cycle, themselves a step up from earlier processors that would take a variable number of cycles to complete any given operation. In a superscalar CPU several functional units of the same type are included, along with additional circuitry to dispatch instructions to the units. For instance most superscalar designs include more than one integer unit (typically referred to as an ALU). The dispatcher reads instructions from memory and decides which ones can be run in parallel, dispatching them to the two units. Performance of the dispatcher is key to the overall performance of a superscalar design. The task is not a simple one, the instructions a = b + c; d = e + f can be run in parallel because none of the results are dependent on other calculations. However the instructions a = b + c; d = a + f may or may not be able to run in parallel, depending on the order in which the instructions complete as they move through the units. Much of modern CPU design is dedicated to increasing the accuracy of the dispatcher system, and allowing it to keep the multiple units in use at all times. This has become increasingly important as the number of units has increased. While early superscalar CPUs would have two ALUs and a single FPU, a modern design like the PowerPC 970 include four ALUs, two FPUs and two SIMD units as well. If the dispatcher is ineffective in keeping all of these units fed with instructions, the performance of the system as a whole will suffer greatly. Superscalar systems were originally implemented on RISC CPUs. This was because the RISC design results in a simple core, allowing several of them to be built onto a single CPU. This was the reason that RISC designs were faster than CISC through the 1980s and into the 1990s, but as the chip manufacturing processes improved, even "complex" designs like the IA-32 were able to go superscalar. Dramatic improvements in the quality of the control unit now appear unlikely, limiting future improvements in speed of the basic superscalar design. One potential solution to this problem is to move the dispatcher logic out of the chip and into the compiler, which can spend considerably more time and effort on making the best decisions possible. This is the basic premise of very long instruction word(VLIW) CPU designs, which is also known as, static superscalar or compile time scheduling. source (http://en.wikipedia.org/wiki/Superscalar) -Balaji zhong_cx said:

Aloha! Quoting zhong_cx zhong_cx@tom.com>: The term "super scalar" is generally associated with processors, not FPGAs. The term normally implies that the processor has the architectural capability to execute more than one instruction/cycle. That is having a IPC (Instruction Per Cycle) greater than 1. The definition is more specifically related to instrcution *issue* which is the event when an instruction is dipatched to the execution units (i.e. ALU, load/store unit, FPU unit etc). Most modern desktop/server processors are superscalar, while most embedded processors are not. The OpenRISC core for example is a *scalar issue* processor core, at least the currently available versions of the core. Since the superscalar behavious (usually) is hidden and the API is the same for both a scalar and a superscalar version it would be possible to extend the OpenRISC architecture to a superscalar design. -- Med vänlig hälsning, Yours Joachim Strömbergson - Alltid i harmonisk svängning. VP, Research & Development ---------------------------------------------------------------------- InformAsic AB / Hugo Grauers gata 5B / SE-411 33 GÖTEBORG / Sweden Tel: +46 31 68 54 90 Fax: +46 31 68 54 91 Mobile: +46 733 75 97 02 E-mail: joachim.strombergson@informasic.com Home: www.informasic.com ----------------------------------------------------------------------