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TAP controller and Debug Interface
by jcastillo on Nov 23, 2004 |
jcastillo
Posts: 32 Joined: Jun 29, 2004 Last seen: Dec 21, 2021 |
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|
Hello:
I have successfully runned eCos over OR1200 on a Celoxica RC203 platform.
Now I am trying to include the debug interface and the TAP controller in the
design.
The platform I developed is based on the orp_soc platform, but the
dbg_interface included on it is quite old and the ports has changed.
With the new tap controller and dbg_interface I don't know how to connect
them together:
Below is part of the code I wrote. How the connections between TAP and
dbg_interface might be?
Best Regards
Javier Castillo
//JTAG ports
jtag_tdi,jtag_tms,jtag_tck,
jtag_tdo,
wire debug_select;
wire debug_tdi;
wire debug_tdo;
wire shift_dr;
wire pause_dr;
wire update_dr;
dbg_top dbg_top (
// JTAG pins
.tck_i ( jtag_tck),
.tdi_i ( debug_tdi),
.tdo_o ( debug_tdo),
.rst_i ( reset ),
// Boundary Scan signals
.shift_dr_i( shift_dr),
.pause_dr_i( pause_dr),
.update_dr_i( update_dr),
.debug_select_i( debug_select) ,
// WISHBONE common
.wb_clk_i ( clk ),
// WISHBONE master interface
.wb_adr_o ( wb_dm_adr_o ),
.wb_dat_i ( wb_dm_dat_i ),
.wb_dat_o ( wb_dm_dat_o ),
.wb_sel_o ( wb_dm_sel_o ),
.wb_we_o ( wb_dm_we_o ),
.wb_stb_o ( wb_dm_stb_o ),
.wb_cyc_o ( wb_dm_cyc_o ),
.wb_cab_o ( wb_dm_cab_o ),
.wb_ack_i ( wb_dm_ack_i ),
.wb_err_i ( wb_dm_err_i ),
.wb_cti_o( ),
.wb_bte_o( ),
// RISC signals
.cpu0_clk_i ( clk ),
.cpu0_addr_o ( dbg_adr ),
.cpu0_data_i ( dbg_dat_risc ),
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o( dbg_stall ),
.cpu0_stb_o ( dbg_op[2] ),
.cpu0_we_o ( dbg_op[0] ),
.cpu0_ack_i ( dbg_ack),
.cpu0_rst_o ( )
);
tap_top tap_top(
.tms_pad_i ( jtag_tms ),
.tck_pad_i ( jtag_tck ),
.trst_pad_i ( reset ),
.tdi_pad_i ( jtag_tdi ),
.tdo_pad_o ( jtag_tdo ),
.tdo_padoe_o( ),
.shift_dr_o ( shift_dr),
.pause_dr_o ( pause_dr),
.update_dr_o ( update_dr),
.capture_dr_o ( ),
.extest_select_o( ),
.sample_preload_select_o( ),
.mbist_select_o( ),
.debug_select_o( debug_select),
.tdo_o( debug_tdi ),
.debug_tdi_i ( debug_tdo), // from debug module
.bs_chain_tdi_i ( 1'b0), // from Boundary Scan Chain
.mbist_tdi_i ( 1'b0) // from Mbist Chain
);
//OpenRISC 1200 Instantiation
or1200_top or1200_top(
// System
.clk_i(clk),
.rst_i(reset),
.pic_ints_i(pic_ints),
.clmode_i(clmode),
// Instruction WISHBONE INTERFACE
//Data WISHBONE INTERFACE
// Debug
.dbg_stall_i ( dbg_stall ),
.dbg_dat_i ( dbg_dat_dbg ),
.dbg_adr_i ( dbg_adr ),
.dbg_ewt_i ( 1'b0 ),
.dbg_lss_o ( dbg_lss ),
.dbg_is_o ( dbg_is ),
.dbg_wp_o ( dbg_wp ),
.dbg_bp_o ( dbg_bp ),
.dbg_dat_o ( dbg_dat_risc ),
.dbg_ack_o ( dbg_ack),
.dbg_stb_i ( dbg_op[2] ),
.dbg_we_i ( dbg_op[0] ),
);
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TAP controller and Debug Interface
by Unknown on Nov 24, 2004 |
Not available! | ||
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There is documentation for the debug module on the opencores website
(for both, old and new version). Take the one you need and If you
can't connect signals after reading it, I'll be glad to help you.
Best regards,
Igor
On Tue, 23 Nov 2004 18:48:13 +0100, jcastillo
jcastillo@opensocdesign.com> wrote:
Hello:
I have successfully runned eCos over OR1200 on a Celoxica RC203 platform.
Now I am trying to include the debug interface and the TAP controller in the
design.
The platform I developed is based on the orp_soc platform, but the
dbg_interface included on it is quite old and the ports has changed.
With the new tap controller and dbg_interface I don't know how to connect
them together:
Below is part of the code I wrote. How the connections between TAP and
dbg_interface might be?
Best Regards
Javier Castillo
//JTAG ports
jtag_tdi,jtag_tms,jtag_tck,
jtag_tdo,
wire debug_select;
wire debug_tdi;
wire debug_tdo;
wire shift_dr;
wire pause_dr;
wire update_dr;
dbg_top dbg_top (
// JTAG pins
.tck_i ( jtag_tck),
.tdi_i ( debug_tdi),
.tdo_o ( debug_tdo),
.rst_i ( reset ),
// Boundary Scan signals
.shift_dr_i( shift_dr),
.pause_dr_i( pause_dr),
.update_dr_i( update_dr),
.debug_select_i( debug_select) ,
// WISHBONE common
.wb_clk_i ( clk ),
// WISHBONE master interface
.wb_adr_o ( wb_dm_adr_o ),
.wb_dat_i ( wb_dm_dat_i ),
.wb_dat_o ( wb_dm_dat_o ),
.wb_sel_o ( wb_dm_sel_o ),
.wb_we_o ( wb_dm_we_o ),
.wb_stb_o ( wb_dm_stb_o ),
.wb_cyc_o ( wb_dm_cyc_o ),
.wb_cab_o ( wb_dm_cab_o ),
.wb_ack_i ( wb_dm_ack_i ),
.wb_err_i ( wb_dm_err_i ),
.wb_cti_o( ),
.wb_bte_o( ),
// RISC signals
.cpu0_clk_i ( clk ),
.cpu0_addr_o ( dbg_adr ),
.cpu0_data_i ( dbg_dat_risc ),
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o( dbg_stall ),
.cpu0_stb_o ( dbg_op[2] ),
.cpu0_we_o ( dbg_op[0] ),
.cpu0_ack_i ( dbg_ack),
.cpu0_rst_o ( )
);
tap_top tap_top(
.tms_pad_i ( jtag_tms ),
.tck_pad_i ( jtag_tck ),
.trst_pad_i ( reset ),
.tdi_pad_i ( jtag_tdi ),
.tdo_pad_o ( jtag_tdo ),
.tdo_padoe_o( ),
.shift_dr_o ( shift_dr),
.pause_dr_o ( pause_dr),
.update_dr_o ( update_dr),
.capture_dr_o ( ),
.extest_select_o( ),
.sample_preload_select_o( ),
.mbist_select_o( ),
.debug_select_o( debug_select),
.tdo_o( debug_tdi ),
.debug_tdi_i ( debug_tdo), // from debug module
.bs_chain_tdi_i ( 1'b0), // from Boundary Scan Chain
.mbist_tdi_i ( 1'b0) // from Mbist Chain
);
//OpenRISC 1200 Instantiation
or1200_top or1200_top(
// System
.clk_i(clk),
.rst_i(reset),
.pic_ints_i(pic_ints),
.clmode_i(clmode),
// Instruction WISHBONE INTERFACE
//Data WISHBONE INTERFACE
// Debug
.dbg_stall_i ( dbg_stall ),
.dbg_dat_i ( dbg_dat_dbg ),
.dbg_adr_i ( dbg_adr ),
.dbg_ewt_i ( 1'b0 ),
.dbg_lss_o ( dbg_lss ),
.dbg_is_o ( dbg_is ),
.dbg_wp_o ( dbg_wp ),
.dbg_bp_o ( dbg_bp ),
.dbg_dat_o ( dbg_dat_risc ),
.dbg_ack_o ( dbg_ack),
.dbg_stb_i ( dbg_op[2] ),
.dbg_we_i ( dbg_op[0] ),
);
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
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TAP controller and Debug Interface
by jcastillo on Nov 24, 2004 |
jcastillo
Posts: 32 Joined: Jun 29, 2004 Last seen: Dec 21, 2021 |
||
|
Hello:
I connect the tap controller and the new dbg interface, but it doesnÂ’t
work with jp1 program. Has anybody used jp1 with the new dbg_interface and
the tap controller?
Regards
Javier Castillo
-----Mensaje original-----
De: openrisc-bounces@opencores.org [mailto:openrisc-bounces@opencores.org]
En nombre de Igor Mohor
Enviado el: miércoles, 24 de noviembre de 2004 8:33
Para: List about OpenRISC project
Asunto: Re: [openrisc] TAP controller and Debug Interface
There is documentation for the debug module on the opencores website
(for both, old and new version). Take the one you need and If you
can't connect signals after reading it, I'll be glad to help you.
Best regards,
Igor
On Tue, 23 Nov 2004 18:48:13 +0100, jcastillo
jcastillo@opensocdesign.com> wrote:
Hello: I have successfully runned eCos over OR1200 on a Celoxica RC203 platform.
Now I am trying to include the debug interface and the TAP controller in
the
design.
The platform I developed is based on the orp_soc platform, but the
dbg_interface included on it is quite old and the ports has changed.
With the new tap controller and dbg_interface I don't know how to connect
them together:
Below is part of the code I wrote. How the connections between TAP and
dbg_interface might be?
Best Regards
Javier Castillo
//JTAG ports
jtag_tdi,jtag_tms,jtag_tck,
jtag_tdo,
wire debug_select;
wire debug_tdi;
wire debug_tdo;
wire shift_dr;
wire pause_dr;
wire update_dr;
dbg_top dbg_top (
// JTAG pins
.tck_i ( jtag_tck),
.tdi_i ( debug_tdi),
.tdo_o ( debug_tdo),
.rst_i ( reset ),
// Boundary Scan signals
.shift_dr_i( shift_dr),
.pause_dr_i( pause_dr),
.update_dr_i( update_dr),
.debug_select_i( debug_select) ,
// WISHBONE common
.wb_clk_i ( clk ),
// WISHBONE master interface
.wb_adr_o ( wb_dm_adr_o ),
.wb_dat_i ( wb_dm_dat_i ),
.wb_dat_o ( wb_dm_dat_o ),
.wb_sel_o ( wb_dm_sel_o ),
.wb_we_o ( wb_dm_we_o ),
.wb_stb_o ( wb_dm_stb_o ),
.wb_cyc_o ( wb_dm_cyc_o ),
.wb_cab_o ( wb_dm_cab_o ),
.wb_ack_i ( wb_dm_ack_i ),
.wb_err_i ( wb_dm_err_i ),
.wb_cti_o( ),
.wb_bte_o( ),
// RISC signals
.cpu0_clk_i ( clk ),
.cpu0_addr_o ( dbg_adr ),
.cpu0_data_i ( dbg_dat_risc ),
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o( dbg_stall ),
.cpu0_stb_o ( dbg_op[2] ),
.cpu0_we_o ( dbg_op[0] ),
.cpu0_ack_i ( dbg_ack),
.cpu0_rst_o ( )
);
tap_top tap_top(
.tms_pad_i ( jtag_tms ),
.tck_pad_i ( jtag_tck ),
.trst_pad_i ( reset ),
.tdi_pad_i ( jtag_tdi ),
.tdo_pad_o ( jtag_tdo ),
.tdo_padoe_o( ),
.shift_dr_o ( shift_dr),
.pause_dr_o ( pause_dr),
.update_dr_o ( update_dr),
.capture_dr_o ( ),
.extest_select_o( ),
.sample_preload_select_o( ),
.mbist_select_o( ),
.debug_select_o( debug_select),
.tdo_o( debug_tdi ),
.debug_tdi_i ( debug_tdo), // from debug module
.bs_chain_tdi_i ( 1'b0), // from Boundary Scan Chain
.mbist_tdi_i ( 1'b0) // from Mbist Chain
);
//OpenRISC 1200 Instantiation
or1200_top or1200_top(
// System
.clk_i(clk),
.rst_i(reset),
.pic_ints_i(pic_ints),
.clmode_i(clmode),
// Instruction WISHBONE INTERFACE
//Data WISHBONE INTERFACE
// Debug
.dbg_stall_i ( dbg_stall ),
.dbg_dat_i ( dbg_dat_dbg ),
.dbg_adr_i ( dbg_adr ),
.dbg_ewt_i ( 1'b0 ),
.dbg_lss_o ( dbg_lss ),
.dbg_is_o ( dbg_is ),
.dbg_wp_o ( dbg_wp ),
.dbg_bp_o ( dbg_bp ),
.dbg_dat_o ( dbg_dat_risc ),
.dbg_ack_o ( dbg_ack),
.dbg_stb_i ( dbg_op[2] ),
.dbg_we_i ( dbg_op[0] ),
);
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
|
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TAP controller and Debug Interface
by DannyBaumann on Nov 25, 2004 |
DannyBaumann
Posts: 4 Joined: Sep 30, 2004 Last seen: Feb 24, 2009 |
||
|
Hello,
you need to use the JP2 program - but you have to comment out dbg_test()
in the main routine if you don't use the SDRAM controller written by
Flextronics.
Below is my (working) wiring. Of course you have to use all the required
wires.
Regards
Danny Baumann
tap_top tap_module(
// JTAG pads
.tms_pad_i ( jtag_tms ),
.tck_pad_i ( jtag_tck ),
.trst_pad_i ( ~jtag_trst ),
.tdi_pad_i ( jtag_tdi ),
.tdo_pad_o ( jtag_tdo ),
.tdo_padoe_o ( ),
// TAP states
.shift_dr_o ( debug_shift_dr ),
.pause_dr_o ( debug_pause_dr ),
.update_dr_o ( debug_update_dr ),
.capture_dr_o ( ),
// Select signals for boundary scan or mbist
.extest_select_o ( ),
.sample_preload_select_o ( ),
.mbist_select_o ( ),
.debug_select_o ( debug_select ),
// TDO signal that is connected to TDI of sub-modules.
.tdo_o ( debug_tdi ),
// TDI signals from sub-modules
.debug_tdi_i ( debug_tdo ),
.bs_chain_tdi_i ( 1'b0 ),
.mbist_tdi_i ( 1'b0 )
);
dbg_top debug_module(
// JTAG signals
.tck_i ( jtag_tck ),
.tdi_i ( debug_tdi ),
.tdo_o ( debug_tdo ),
.rst_i ( wb_rst ),
// TAP states
.shift_dr_i ( debug_shift_dr ),
.pause_dr_i ( debug_pause_dr ),
.update_dr_i ( debug_update_dr ),
// Instructions
.debug_select_i ( debug_select ),
// WISHBONE signals
.wb_clk_i ( wb_clk ),
.wb_adr_o ( wbm_debug_adr_o ),
.wb_dat_o ( wbm_debug_dat_o ),
.wb_dat_i ( wbm_debug_dat_i ),
.wb_cyc_o ( wbm_debug_cyc_o ),
.wb_stb_o ( wbm_debug_stb_o ),
.wb_sel_o ( wbm_debug_sel_o ),
.wb_we_o ( wbm_debug_we_o ),
.wb_ack_i ( wbm_debug_ack_i ),
.wb_cab_o ( ),
.wb_err_i ( wbm_debug_err_i ),
.wb_cti_o ( ),
.wb_bte_o ( ),
// CPU signals
.cpu0_clk_i ( wb_clk ),
.cpu0_addr_o ( dbg_adr ),
.cpu0_data_i ( dbg_dat_risc ),
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o ( dbg_stall ),
.cpu0_stb_o ( dbg_stb ),
.cpu0_we_o ( dbg_we ),
.cpu0_ack_i ( dbg_ack ),
.cpu0_rst_o ( )
);
//
// Instantiation of the OR1200 RISC
//
or1200_top or1200_top (
// Common
.rst_i ( wb_rst ),
.clk_i ( clk ),
.clmode_i ( 2'b00 ),
// WISHBONE Instruction Master
.iwb_clk_i ( wb_clk ),
.iwb_rst_i ( wb_rst ),
.iwb_cyc_o ( wbm_cpui_cyc_o ),
.iwb_adr_o ( wbm_cpui_adr_o ),
.iwb_dat_i ( wbm_cpui_dat_i ),
.iwb_dat_o ( wbm_cpui_dat_o ),
.iwb_sel_o ( wbm_cpui_sel_o ),
.iwb_ack_i ( wbm_cpui_ack_i ),
.iwb_err_i ( wbm_cpui_err_i ),
.iwb_rty_i ( wbm_cpui_rty_i ),
.iwb_we_o ( wbm_cpui_we_o ),
.iwb_stb_o ( wbm_cpui_stb_o ),
// WISHBONE Data Master
.dwb_clk_i ( wb_clk ),
.dwb_rst_i ( wb_rst ),
.dwb_cyc_o ( wbm_cpud_cyc_o ),
.dwb_adr_o ( wbm_cpud_adr_o ),
.dwb_dat_i ( wbm_cpud_dat_i ),
.dwb_dat_o ( wbm_cpud_dat_o ),
.dwb_sel_o ( wbm_cpud_sel_o ),
.dwb_ack_i ( wbm_cpud_ack_i ),
.dwb_err_i ( wbm_cpud_err_i ),
.dwb_rty_i ( wbm_cpud_rty_i ),
.dwb_we_o ( wbm_cpud_we_o ),
.dwb_stb_o ( wbm_cpud_stb_o ),
// Debug
.dbg_stall_i ( dbg_stall ),
.dbg_dat_i ( dbg_dat_dbg ),
.dbg_adr_i ( dbg_adr ),
.dbg_ewt_i ( 1'b0 ),
.dbg_lss_o ( ),
.dbg_is_o ( ),
.dbg_wp_o ( ),
.dbg_bp_o ( dbg_bp ),
.dbg_dat_o ( dbg_dat_risc ),
.dbg_ack_o ( dbg_ack ),
.dbg_stb_i ( dbg_stb ),
.dbg_we_i ( dbg_we ),
// Power Management
.pm_clksd_o ( ),
.pm_cpustall_i ( 1'b0 ),
.pm_dc_gate_o ( ),
.pm_ic_gate_o ( ),
.pm_dmmu_gate_o ( ),
.pm_immu_gate_o ( ),
.pm_tt_gate_o ( ),
.pm_cpu_gate_o ( ),
.pm_wakeup_o ( ),
.pm_lvolt_o ( ),
// Interrupts
.pic_ints_i ( ints )
);
jcastillo wrote:
Hello:
I connect the tap controller and the new dbg interface, but it doesn’t
work with jp1 program. Has anybody used jp1 with the new dbg_interface and
the tap controller?
Regards
Javier Castillo
-----Mensaje original-----
De: openrisc-bounces@opencores.org [mailto:openrisc-bounces@opencores.org]
En nombre de Igor Mohor
Enviado el: miércoles, 24 de noviembre de 2004 8:33
Para: List about OpenRISC project
Asunto: Re: [openrisc] TAP controller and Debug Interface
There is documentation for the debug module on the opencores website
(for both, old and new version). Take the one you need and If you
can't connect signals after reading it, I'll be glad to help you.
Best regards,
Igor
On Tue, 23 Nov 2004 18:48:13 +0100, jcastillo
jcastillo@opensocdesign.com> wrote:
Hello: I have successfully runned eCos over OR1200 on a Celoxica RC203 platform.
Now I am trying to include the debug interface and the TAP controller in
the
design.
The platform I developed is based on the orp_soc platform, but the
dbg_interface included on it is quite old and the ports has changed.
With the new tap controller and dbg_interface I don't know how to connect
them together:
Below is part of the code I wrote. How the connections between TAP and
dbg_interface might be?
Best Regards
Javier Castillo
//JTAG ports
jtag_tdi,jtag_tms,jtag_tck,
jtag_tdo,
wire debug_select;
wire debug_tdi;
wire debug_tdo;
wire shift_dr;
wire pause_dr;
wire update_dr;
dbg_top dbg_top (
// JTAG pins
.tck_i ( jtag_tck),
.tdi_i ( debug_tdi),
.tdo_o ( debug_tdo),
.rst_i ( reset ),
// Boundary Scan signals
.shift_dr_i( shift_dr),
.pause_dr_i( pause_dr),
.update_dr_i( update_dr),
.debug_select_i( debug_select) ,
// WISHBONE common
.wb_clk_i ( clk ),
// WISHBONE master interface
.wb_adr_o ( wb_dm_adr_o ),
.wb_dat_i ( wb_dm_dat_i ),
.wb_dat_o ( wb_dm_dat_o ),
.wb_sel_o ( wb_dm_sel_o ),
.wb_we_o ( wb_dm_we_o ),
.wb_stb_o ( wb_dm_stb_o ),
.wb_cyc_o ( wb_dm_cyc_o ),
.wb_cab_o ( wb_dm_cab_o ),
.wb_ack_i ( wb_dm_ack_i ),
.wb_err_i ( wb_dm_err_i ),
.wb_cti_o( ),
.wb_bte_o( ),
// RISC signals
.cpu0_clk_i ( clk ),
.cpu0_addr_o ( dbg_adr ),
.cpu0_data_i ( dbg_dat_risc ),
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o( dbg_stall ),
.cpu0_stb_o ( dbg_op[2] ),
.cpu0_we_o ( dbg_op[0] ),
.cpu0_ack_i ( dbg_ack),
.cpu0_rst_o ( )
);
tap_top tap_top(
.tms_pad_i ( jtag_tms ),
.tck_pad_i ( jtag_tck ),
.trst_pad_i ( reset ),
.tdi_pad_i ( jtag_tdi ),
.tdo_pad_o ( jtag_tdo ),
.tdo_padoe_o( ),
.shift_dr_o ( shift_dr),
.pause_dr_o ( pause_dr),
.update_dr_o ( update_dr),
.capture_dr_o ( ),
.extest_select_o( ),
.sample_preload_select_o( ),
.mbist_select_o( ),
.debug_select_o( debug_select),
.tdo_o( debug_tdi ),
.debug_tdi_i ( debug_tdo), // from debug module
.bs_chain_tdi_i ( 1'b0), // from Boundary Scan Chain
.mbist_tdi_i ( 1'b0) // from Mbist Chain
);
//OpenRISC 1200 Instantiation
or1200_top or1200_top(
// System
.clk_i(clk),
.rst_i(reset),
.pic_ints_i(pic_ints),
.clmode_i(clmode),
// Instruction WISHBONE INTERFACE
//Data WISHBONE INTERFACE
// Debug
.dbg_stall_i ( dbg_stall ),
.dbg_dat_i ( dbg_dat_dbg ),
.dbg_adr_i ( dbg_adr ),
.dbg_ewt_i ( 1'b0 ),
.dbg_lss_o ( dbg_lss ),
.dbg_is_o ( dbg_is ),
.dbg_wp_o ( dbg_wp ),
.dbg_bp_o ( dbg_bp ),
.dbg_dat_o ( dbg_dat_risc ),
.dbg_ack_o ( dbg_ack),
.dbg_stb_i ( dbg_op[2] ),
.dbg_we_i ( dbg_op[0] ),
);
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
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TAP controller and Debug Interface
by jcastillo on Nov 25, 2004 |
jcastillo
Posts: 32 Joined: Jun 29, 2004 Last seen: Dec 21, 2021 |
||
|
Hello:
Thank you very much, my OR1200 is running over a Celoxica RC203 board. I
will add some features and clean the code and I will upload it to OpenCores
CVS is anyone is interested on it.
Just one comment, with gdb 5.3 I get an error "Debug group should be
available in the or1k implementation". I read in the forum that is because a
old definition file in gdb5.3. With gdb5.0 or1200 works fine, so can anybody
correct this old definition file.
Best Regards
Javier Castillo
jcastillo@opensocdesign.com
www.opensocdesign.com
-----Mensaje original-----
De: openrisc-bounces@opencores.org [mailto:openrisc-bounces@opencores.org]
En nombre de Danny Baumann
Enviado el: jueves, 25 de noviembre de 2004 8:00
Para: List about OpenRISC project
Asunto: Re: [openrisc] TAP controller and Debug Interface
Hello,
you need to use the JP2 program - but you have to comment out dbg_test()
in the main routine if you don't use the SDRAM controller written by
Flextronics.
Below is my (working) wiring. Of course you have to use all the required
wires.
Regards
Danny Baumann
tap_top tap_module(
// JTAG pads
.tms_pad_i ( jtag_tms ),
.tck_pad_i ( jtag_tck ),
.trst_pad_i ( ~jtag_trst ),
.tdi_pad_i ( jtag_tdi ),
.tdo_pad_o ( jtag_tdo ),
.tdo_padoe_o ( ),
// TAP states
.shift_dr_o ( debug_shift_dr ),
.pause_dr_o ( debug_pause_dr ),
.update_dr_o ( debug_update_dr ),
.capture_dr_o ( ),
// Select signals for boundary scan or mbist
.extest_select_o ( ),
.sample_preload_select_o ( ),
.mbist_select_o ( ),
.debug_select_o ( debug_select ),
// TDO signal that is connected to TDI of sub-modules.
.tdo_o ( debug_tdi ),
// TDI signals from sub-modules
.debug_tdi_i ( debug_tdo ),
.bs_chain_tdi_i ( 1'b0 ),
.mbist_tdi_i ( 1'b0 )
);
dbg_top debug_module(
// JTAG signals
.tck_i ( jtag_tck ),
.tdi_i ( debug_tdi ),
.tdo_o ( debug_tdo ),
.rst_i ( wb_rst ),
// TAP states
.shift_dr_i ( debug_shift_dr ),
.pause_dr_i ( debug_pause_dr ),
.update_dr_i ( debug_update_dr ),
// Instructions
.debug_select_i ( debug_select ),
// WISHBONE signals
.wb_clk_i ( wb_clk ),
.wb_adr_o ( wbm_debug_adr_o ),
.wb_dat_o ( wbm_debug_dat_o ),
.wb_dat_i ( wbm_debug_dat_i ),
.wb_cyc_o ( wbm_debug_cyc_o ),
.wb_stb_o ( wbm_debug_stb_o ),
.wb_sel_o ( wbm_debug_sel_o ),
.wb_we_o ( wbm_debug_we_o ),
.wb_ack_i ( wbm_debug_ack_i ),
.wb_cab_o ( ),
.wb_err_i ( wbm_debug_err_i ),
.wb_cti_o ( ),
.wb_bte_o ( ),
// CPU signals
.cpu0_clk_i ( wb_clk ),
.cpu0_addr_o ( dbg_adr ),
.cpu0_data_i ( dbg_dat_risc ),
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o ( dbg_stall ),
.cpu0_stb_o ( dbg_stb ),
.cpu0_we_o ( dbg_we ),
.cpu0_ack_i ( dbg_ack ),
.cpu0_rst_o ( )
);
//
// Instantiation of the OR1200 RISC
//
or1200_top or1200_top (
// Common
.rst_i ( wb_rst ),
.clk_i ( clk ),
.clmode_i ( 2'b00 ),
// WISHBONE Instruction Master
.iwb_clk_i ( wb_clk ),
.iwb_rst_i ( wb_rst ),
.iwb_cyc_o ( wbm_cpui_cyc_o ),
.iwb_adr_o ( wbm_cpui_adr_o ),
.iwb_dat_i ( wbm_cpui_dat_i ),
.iwb_dat_o ( wbm_cpui_dat_o ),
.iwb_sel_o ( wbm_cpui_sel_o ),
.iwb_ack_i ( wbm_cpui_ack_i ),
.iwb_err_i ( wbm_cpui_err_i ),
.iwb_rty_i ( wbm_cpui_rty_i ),
.iwb_we_o ( wbm_cpui_we_o ),
.iwb_stb_o ( wbm_cpui_stb_o ),
// WISHBONE Data Master
.dwb_clk_i ( wb_clk ),
.dwb_rst_i ( wb_rst ),
.dwb_cyc_o ( wbm_cpud_cyc_o ),
.dwb_adr_o ( wbm_cpud_adr_o ),
.dwb_dat_i ( wbm_cpud_dat_i ),
.dwb_dat_o ( wbm_cpud_dat_o ),
.dwb_sel_o ( wbm_cpud_sel_o ),
.dwb_ack_i ( wbm_cpud_ack_i ),
.dwb_err_i ( wbm_cpud_err_i ),
.dwb_rty_i ( wbm_cpud_rty_i ),
.dwb_we_o ( wbm_cpud_we_o ),
.dwb_stb_o ( wbm_cpud_stb_o ),
// Debug
.dbg_stall_i ( dbg_stall ),
.dbg_dat_i ( dbg_dat_dbg ),
.dbg_adr_i ( dbg_adr ),
.dbg_ewt_i ( 1'b0 ),
.dbg_lss_o ( ),
.dbg_is_o ( ),
.dbg_wp_o ( ),
.dbg_bp_o ( dbg_bp ),
.dbg_dat_o ( dbg_dat_risc ),
.dbg_ack_o ( dbg_ack ),
.dbg_stb_i ( dbg_stb ),
.dbg_we_i ( dbg_we ),
// Power Management
.pm_clksd_o ( ),
.pm_cpustall_i ( 1'b0 ),
.pm_dc_gate_o ( ),
.pm_ic_gate_o ( ),
.pm_dmmu_gate_o ( ),
.pm_immu_gate_o ( ),
.pm_tt_gate_o ( ),
.pm_cpu_gate_o ( ),
.pm_wakeup_o ( ),
.pm_lvolt_o ( ),
// Interrupts
.pic_ints_i ( ints )
);
jcastillo wrote:
Hello:
I connect the tap controller and the new dbg interface, but it doesnÂ’t
work with jp1 program. Has anybody used jp1 with the new dbg_interface and
the tap controller?
Regards
Javier Castillo
-----Mensaje original-----
De: openrisc-bounces@opencores.org [mailto:openrisc-bounces@opencores.org]
En nombre de Igor Mohor
Enviado el: miércoles, 24 de noviembre de 2004 8:33
Para: List about OpenRISC project
Asunto: Re: [openrisc] TAP controller and Debug Interface
There is documentation for the debug module on the opencores website
(for both, old and new version). Take the one you need and If you
can't connect signals after reading it, I'll be glad to help you.
Best regards,
Igor
On Tue, 23 Nov 2004 18:48:13 +0100, jcastillo
jcastillo@opensocdesign.com> wrote:
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
Hello: I have successfully runned eCos over OR1200 on a Celoxica RC203 platform.
Now I am trying to include the debug interface and the TAP controller in
the
design.
The platform I developed is based on the orp_soc platform, but the
dbg_interface included on it is quite old and the ports has changed.
With the new tap controller and dbg_interface I don't know how to connect
them together:
Below is part of the code I wrote. How the connections between TAP and
dbg_interface might be?
Best Regards
Javier Castillo
//JTAG ports
jtag_tdi,jtag_tms,jtag_tck,
jtag_tdo,
wire debug_select;
wire debug_tdi;
wire debug_tdo;
wire shift_dr;
wire pause_dr;
wire update_dr;
dbg_top dbg_top (
// JTAG pins
.tck_i ( jtag_tck),
.tdi_i ( debug_tdi),
.tdo_o ( debug_tdo),
.rst_i ( reset ),
// Boundary Scan signals
.shift_dr_i( shift_dr),
.pause_dr_i( pause_dr),
.update_dr_i( update_dr),
.debug_select_i( debug_select) ,
// WISHBONE common
.wb_clk_i ( clk ),
// WISHBONE master interface
.wb_adr_o ( wb_dm_adr_o ),
.wb_dat_i ( wb_dm_dat_i ),
.wb_dat_o ( wb_dm_dat_o ),
.wb_sel_o ( wb_dm_sel_o ),
.wb_we_o ( wb_dm_we_o ),
.wb_stb_o ( wb_dm_stb_o ),
.wb_cyc_o ( wb_dm_cyc_o ),
.wb_cab_o ( wb_dm_cab_o ),
.wb_ack_i ( wb_dm_ack_i ),
.wb_err_i ( wb_dm_err_i ),
.wb_cti_o( ),
.wb_bte_o( ),
// RISC signals
.cpu0_clk_i ( clk ),
.cpu0_addr_o ( dbg_adr ),
.cpu0_data_i ( dbg_dat_risc ),
.cpu0_data_o ( dbg_dat_dbg ),
.cpu0_bp_i ( dbg_bp ),
.cpu0_stall_o( dbg_stall ),
.cpu0_stb_o ( dbg_op[2] ),
.cpu0_we_o ( dbg_op[0] ),
.cpu0_ack_i ( dbg_ack),
.cpu0_rst_o ( )
);
tap_top tap_top(
.tms_pad_i ( jtag_tms ),
.tck_pad_i ( jtag_tck ),
.trst_pad_i ( reset ),
.tdi_pad_i ( jtag_tdi ),
.tdo_pad_o ( jtag_tdo ),
.tdo_padoe_o( ),
.shift_dr_o ( shift_dr),
.pause_dr_o ( pause_dr),
.update_dr_o ( update_dr),
.capture_dr_o ( ),
.extest_select_o( ),
.sample_preload_select_o( ),
.mbist_select_o( ),
.debug_select_o( debug_select),
.tdo_o( debug_tdi ),
.debug_tdi_i ( debug_tdo), // from debug module
.bs_chain_tdi_i ( 1'b0), // from Boundary Scan Chain
.mbist_tdi_i ( 1'b0) // from Mbist Chain
);
//OpenRISC 1200 Instantiation
or1200_top or1200_top(
// System
.clk_i(clk),
.rst_i(reset),
.pic_ints_i(pic_ints),
.clmode_i(clmode),
// Instruction WISHBONE INTERFACE
//Data WISHBONE INTERFACE
// Debug
.dbg_stall_i ( dbg_stall ),
.dbg_dat_i ( dbg_dat_dbg ),
.dbg_adr_i ( dbg_adr ),
.dbg_ewt_i ( 1'b0 ),
.dbg_lss_o ( dbg_lss ),
.dbg_is_o ( dbg_is ),
.dbg_wp_o ( dbg_wp ),
.dbg_bp_o ( dbg_bp ),
.dbg_dat_o ( dbg_dat_risc ),
.dbg_ack_o ( dbg_ack),
.dbg_stb_i ( dbg_op[2] ),
.dbg_we_i ( dbg_op[0] ),
);
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
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