Dear Helpers, I integrated and generated a netlist for a new processor. I included in the top module two small separate instructions and data memories. My question is, when I will download the "optimized chip" to the Altera STRATIX device, that I already have, do I need to remove these memories or I include them and download the whole chip into the device? Also, I am wondering if I remove these modules how can I test the design later? That, is I need to run some Benchmarks and the binaries must be somewhere! Please notice that the PCI Development kit I have (+ Stratix device) has an SDRAM on it? Thank you so much for your help, /Ben UEC-IS -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/openrisc/attachments/20041208/004a6178/attachment-0001.htm