Dear all,

I'm just new in this nice project of OpenRisc and so I have to make some
skill.
I have to develop a multiprocessor application and so I was looking for
the best
architecture on which my system should be based.
It is very attractive to use an OpenCore IP, and so I would like to use
this processor
in my research activity.
I was wondering if the OpenRisc Architectural simulator has a
cycle-accurate ISS.
I would also like to know what do you think on possibility of creating a
multiprocessor OpenRisc
environment.

Regards.

Sergio Tota

* Sergio Tota (sergio.tota@polito.it) wrote:

all instructions in architectual simulator are executed in 1 cycle but
this is not the case for all (just most) instructions in or1200 implementation.

having said that, architectual simulator does take
into account different cache and mmu models. in fact,
architectual simulator should be cycle accurate for OpenRisc processor
implementation that executes all instructions in 1 cycle. any difference
would infact be considered a bug.

regards,
p.