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ARM7 vs OpenRisc
by Unknown on Dec 20, 2004 		Not available!
Hi,

I'm looking for a replacement of an AMR7 processor, I was
really impressed by the OpenRisc 1000 processor but it looks
quite bugger since it has MMU and Caches capability
that I don't neet.

So, is someone able to suggest me a solution to replace my ARM
with an "open" solution? Is there any way to use the OpenRisc1000
in a dummy mode, meaning for example the possibility to exclude
MMU and cache from the RTL code?

Any gate counts figure about OpenRisc1000, as such, would
be available also.

Thanks in advance for your advises.

Best Regards
Stefano
ARM7 vs OpenRisc
by zhustudio on Dec 20, 2004 		zhustudio
Posts: 15
Joined: Sep 1, 2008
Last seen: May 21, 2022
hi stefano the or1k is better than arm7 coz of the opensource. and u can comment line in or1200_define.v to disable MMU and Cache. good luck zhu stefano.lorenzini1@tin.it wrote:
Hi, I'm looking for a replacement of an AMR7 processor, I was really impressed by the OpenRisc 1000 processor but it looks quite bugger since it has MMU and Caches capability that I don't neet. So, is someone able to suggest me a solution to replace my ARM with an "open" solution? Is there any way to use the OpenRisc1000 in a dummy mode, meaning for example the possibility to exclude MMU and cache from the RTL code? Any gate counts figure about OpenRisc1000, as such, would be available also. Thanks in advance for your advises. Best Regards Stefano _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc



ARM7 vs OpenRisc
by Unknown on Dec 20, 2004 		Not available!
On Monday 20 December 2004 01:05 pm, stefano.lorenzini1@tin.it wrote:
quite bugger since it has MMU and Caches capability
that I don't neet.


You can disable all of these in the configuration file... (:

So, is someone able to suggest me a solution to replace my ARM
MMU and cache from the RTL code?


Yes... just edit a few define's... just download the codes and look for
yourself.. (:

cheers..

with metta,
shawn tan.

ARM7 vs OpenRisc
by Unknown on Dec 21, 2004 		Not available!
You can "disable" MMU and Caches prior to synthesis, so you will not have them in the implemented version. Likewise you can "disable" other units, and even some instructions (like division instructions, rorate, mac etc etc). This should make OR1200 about the same size as ARM7... regards, Damjan ----- Original Message ----- From: stefano.lorenzini1@tin.it> To: openrisc@opencores.org> Sent: Monday, December 20, 2004 2:05 PM Subject: [openrisc] ARM7 vs OpenRisc
Hi, I'm looking for a replacement of an AMR7 processor, I was really impressed by the OpenRisc 1000 processor but it looks quite bugger since it has MMU and Caches capability that I don't neet. So, is someone able to suggest me a solution to replace my ARM with an "open" solution? Is there any way to use the OpenRisc1000 in a dummy mode, meaning for example the possibility to exclude MMU and cache from the RTL code? Any gate counts figure about OpenRisc1000, as such, would be available also. Thanks in advance for your advises. Best Regards Stefano _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc




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