Hi, I am working on the or1k benchmarking. What I did is using the same
application C programs, compiling them and runing them on various core
simulators. The number I got with the or1k is much larger than other
avaiable processor cores, which seems to me is not reasonable.

Here is an example, I have the following FIR C program
==================
for (i=128;i dout = 0;
for (j=0;j dout = dout + datain[i-j]*coeff[j];
}
==================

I firstly use the gcc compiler and ld to get the objective code. Then I
use the "or32-uclinux-sim --enable-profiler ..". After that I use "or32-
uclinux-sim profiler -c". The report shows that the above code require
72 Million cycles ! It is so high than it almost equals to 100 times of
others' number. Looking at the code, it actually only has 2048*128*2 =
500K operations. Are the overhead too large ?

Is something wrong in using the toolchain ? or the simulator didnot give
a correct result ?

thanks

Hello: How do you compile the code? Do you use -O2? It seems like if the multiplication is being done by software. Javier Castillo -----Mensaje original----- De: openrisc-bounces@opencores.org [mailto:openrisc-bounces@opencores.org] En nombre de zhang_lsv@yahoo.com Enviado el: lunes, 20 de diciembre de 2004 19:10 Para: openrisc@opencores.org Asunto: [openrisc] OpenRisc Benchmarking Hi, I am working on the or1k benchmarking. What I did is using the same application C programs, compiling them and runing them on various core simulators. The number I got with the or1k is much larger than other avaiable processor cores, which seems to me is not reasonable. Here is an example, I have the following FIR C program ================== for (i=128;ihttp://www.opencores.org/mailman/listinfo/openrisc

I borrowed the Makefile from the testbench in the 'sim' package. It seems not using O2 option there. Now I added -O3, and the number of cycles has decreased to 7 Million, which is still 8-9 times larger than others. Do any other options I can play with ? In addition to the number of cycles, how can I know the "number of total instructions" so that I can compute "IPC"? thanks Zhang ----- Original Message ----- From: jcastillojcastillo@o...> To: Date: Mon Dec 20 19:40:38 CET 2004 Subject: [openrisc] OpenRisc Benchmarking

* zhang_lsv@yahoo.com (zhang_lsv@yahoo.com) wrote:

try also -fomit-frame-pointer and be sure configure memory delays to 0
in the sim.cfg.

the code you have looks simple enough so i'd investigate the assembler
to chack for hardware muls and the the code seams reasonable...

regards,
p.

Hi, Matjaz, I found if I set the Flash Memory delayr = 2 (original is 10), the number of cycles can be heavily decreased. But is such setting reasonable ? Why is the default value 10 ? And How to get the number of instructions totally ? thanks ----- Original Message ----- From: Matjaz Breskvarphoenix@o...> To: Date: Mon Dec 20 23:18:45 CET 2004 Subject: [openrisc] OpenRisc Benchmarking

* Zhang Yong (zhang_lsv@yahoo.com) wrote:

well depends on the memory... if you have sram this is more
than reasonable. also, please bear in mind the this is without the
cache. (and on other platforms you probably have cache)

so i'd suggest you pick the same cache hit/miss delay and cache type and
then compare...



This is very simple. i think i defined 'l.nop 15' to reset the
counters and when you're done with the test you issue 'l.nop 1' and when
simulator exits it will print nr. of cycles and instructions...

regards,
p.