I have implemented the new debug interface on my soc, but I have
problems with jp2.

I can successfully stall and unstall the processor by issuing a
dbg_cpu0_write_ctrl(0, 0x01) and dbg_cpu0_write_ctrl(0, 0x00). I can
also issue a dbg_wb_write32, but only once. Every other command gives
me the following output:

RETRY
RETRY
RETRY
RETRY
JTAG ID =
RETRY
RETRY
RETRY
RETRY
JTAG ID =

and so forth. I'v read that others had problems using the jp2 program
also, haw did you fix the problem? Would some debug detailed debug
messages help to identify the problem?

thanks

You may want to double check 1) The memory (internal/external) SRAM/ registers 2) Connectivity My 2 cents, Farhan ----- Original Message ----- From: Markus Lendmarkus.lend@g...> To: Date: Tue Jan 4 18:01:24 CET 2005 Subject: [openrisc] New debug interface and JP2

Hello, I recommend you to take a look to openrisc 1200 over a celoxica rc203 board. You can find it under the rc203 directory inside the or1k project. It uses the new debug interface and the tap controller. Compare it with yours to see if everything is well connected. Best Regards Javier Castillo jcastillo@opensocdesign.com www.opensocdesign.com -----Mensaje original----- De: openrisc-bounces@opencores.org [mailto:openrisc-bounces@opencores.org] En nombre de farhan@vt.edu Enviado el: miércoles, 05 de enero de 2005 22:32 Para: markus.lend@gmail.com; openrisc@opencores.org Asunto: Re: [openrisc] New debug interface and JP2 You may want to double check 1) The memory (internal/external) SRAM/ registers 2) Connectivity My 2 cents, Farhan ----- Original Message ----- From: Markus Lendmarkus.lend@g...> To: Date: Tue Jan 4 18:01:24 CET 2005 Subject: [openrisc] New debug interface and JP2 _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc