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ORPSoC JTAG pin assignment by Unknown on Jan 12, 2005			Not available!
Dear Sir, I have followed the instructions of Basic Custom ORPSoC HW tutorial and software tutorial.I have been trying to communicate with my design on board through the parallel port and jp1 server. It has failed. Iam using a Virtex2 (xcv1000FG456) FPGA. Can you please suggest the pin assignments for the jtag pins of the ORPSoC design? I tried using the jtag pins on the FPGA which are c19(TCK),D3(TDI), D20 (TDO), B20(TMS). But it is giving DRC errors in Xilinx ISE PACE. Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx spartan3 Parallel port JTAG cable which we modified with flying leads to fit to RC200 board to establish the communication. The modified cable works fine with the Xilinx impact and detects the JTAG chain.What implications can this have on my design not working? Really would appreciate any sort of help ASAP........... Thanks in advance for your support... Best Regards Sona Dear Sir, I have followed the instructions of Basic Custom ORPSoC HW tutorial and software tutorial.I have been trying to communicate with my design on board through the parallel port and jp1 server. It has failed. Iam using a Virtex2 (xcv1000FG456) FPGA. Can you please suggest the pin assignments for the jtag pins of the ORPSoC design? I tried using the jtag pins on the FPGA which are c19(TCK),D3(TDI), D20 (TDO), B20(TMS). But it is giving DRC errors in Xilinx ISE PACE. Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx spartan3 Parallel port JTAG cable which we modified with flying leads to fit to RC200 board to establish the communication. The modified cable works fine with the Xilinx impact and detects the JTAG chain.What implications can this have on my design not working? Really would appreciate any sort of help ASAP........... Thanks in advance for your support... Best Regards Sona

ORPSoC JTAG pin assignment by jcastillo on Jan 13, 2005			jcastillo Posts: 32 Joined: Jun 29, 2004 Last seen: Dec 21, 2021
[q]Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx spartan3 Parallel port JTAG cable which we modified with flying leads to fit to RC200 board to establish the communication. The modified cable works fine with the Xilinx impact and detects the JTAG chain.What implications can this have on my design not working?[/q] [q]Really would appreciate any sort of help ASAP........... Thanks in advance for your support... Best Regards Sona[/q] The ucf files are prepared to connect the parallel cable to the expansion header, take a look to it to see how to connect them. To program the FPGA use the FTU program provided by Celoxica or use another JTAG cable connected to the JTAG header to program the FPGA. Best Regards Javier Castillo <A HREF="mailto:jcastillo@opensocdesign.com">jcastillo@opensocdesign.com</A> _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx spartan3 Parallel port JTAG cable which we modified with flying leads to fit to RC200 board to establish the communication. The modified cable works fine with the Xilinx impact and detects the JTAG chain.What implications can this have on my design not working? Really would appreciate any sort of help ASAP........... Thanks in advance for your support... Best Regards Sona The ucf files are prepared to connect the parallel cable to the expansion header, take a look to it to see how to connect them. To program the FPGA use the FTU program provided by Celoxica or use another JTAG cable connected to the JTAG header to program the FPGA. Best Regards Javier Castillo jcastillo@opensocdesign.com _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

ORPSoC JTAG pin assignment by Unknown on Jan 13, 2005			Not available!
I had the same problem. I solved it by using io-pins (H2, J2, K2, E4... on Memec's card) as JTAG-port. First load the design into the Virtex-II using the "normal" JTAG-port then move the cable to the pins that you assigned. Patrik ----- Original Message ----- From: <A HREF="mailto:sonatomy@y...">sonatomy@y...</A><<A HREF="mailto:sonatomy@y...">sonatomy@y...</A>> To: Date: Wed Jan 12 20:53:12 CET 2005 Subject: [openrisc] ORPSoC JTAG pin assignment [q] Dear Sir, I have followed the instructions of Basic Custom ORPSoC HW tutorial and software tutorial.I have been trying to communicate with my design on board through the parallel port and jp1 server. It has failed. Iam using a Virtex2 (xcv1000FG456) FPGA. Can you please suggest the pin assignments for the jtag pins of the ORPSoC design? I tried using the jtag pins on the FPGA which are c19(TCK),D3(TDI), D20 (TDO), B20(TMS). But it is giving DRC errors in Xilinx ISE PACE. Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx spartan3 Parallel port JTAG cable which we modified with flying leads to fit to RC200 board to establish the communication. The modified cable works fine with the Xilinx impact and detects the JTAG chain.What implications can this have on my design not working? Really would appreciate any sort of help ASAP........... Thanks in advance for your support... Best Regards Sona [/q] I had the same problem. I solved it by using io-pins (H2, J2, K2, E4... on Memec's card) as JTAG-port. First load the design into the Virtex-II using the "normal" JTAG-port then move the cable to the pins that you assigned. Patrik ----- Original Message ----- From: sonatomy@y...sonatomy@y...> To: Date: Wed Jan 12 20:53:12 CET 2005 Subject: [openrisc] ORPSoC JTAG pin assignment Dear Sir, I have followed the instructions of Basic Custom ORPSoC HW tutorial and software tutorial.I have been trying to communicate with my design on board through the parallel port and jp1 server. It has failed. Iam using a Virtex2 (xcv1000FG456) FPGA. Can you please suggest the pin assignments for the jtag pins of the ORPSoC design? I tried using the jtag pins on the FPGA which are c19(TCK),D3(TDI), D20 (TDO), B20(TMS). But it is giving DRC errors in Xilinx ISE PACE. Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx spartan3 Parallel port JTAG cable which we modified with flying leads to fit to RC200 board to establish the communication. The modified cable works fine with the Xilinx impact and detects the JTAG chain.What implications can this have on my design not working? Really would appreciate any sort of help ASAP........... Thanks in advance for your support... Best Regards Sona

ORPSoC JTAG pin assignment by Unknown on Jan 13, 2005			Not available!
Of course you got the DRC errors. TCK, TDI, TDO and TMS are reserved pins (used when internal JTAG is used). You need to take any other (general purpose in/out pins). Regards, Igor On Wed, 12 Jan 2005 20:53:12 +0100, <A HREF="mailto:sonatomy@yahoo.com">sonatomy@yahoo.com</A> <<A HREF="mailto:sonatomy@yahoo.com">sonatomy@yahoo.com</A>> wrote: [q] Dear Sir, I have followed the instructions of Basic Custom ORPSoC HW tutorial and software tutorial.I have been trying to communicate with my design on board through the parallel port and jp1 server. It has failed. Iam using a Virtex2 (xcv1000FG456) FPGA. Can you please suggest the pin assignments for the jtag pins of the ORPSoC design? I tried using the jtag pins on the FPGA which are c19(TCK),D3(TDI), D20 (TDO), B20(TMS). But it is giving DRC errors in Xilinx ISE PACE. Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx spartan3 Parallel port JTAG cable which we modified with flying leads to fit to RC200 board to establish the communication. The modified cable works fine with the Xilinx impact and detects the JTAG chain.What implications can this have on my design not working? Really would appreciate any sort of help ASAP........... Thanks in advance for your support... Best Regards Sona _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> [/q] Of course you got the DRC errors. TCK, TDI, TDO and TMS are reserved pins (used when internal JTAG is used). You need to take any other (general purpose in/out pins). Regards, Igor On Wed, 12 Jan 2005 20:53:12 +0100, sonatomy@yahoo.com sonatomy@yahoo.com> wrote: Dear Sir, I have followed the instructions of Basic Custom ORPSoC HW tutorial and software tutorial.I have been trying to communicate with my design on board through the parallel port and jp1 server. It has failed. Iam using a Virtex2 (xcv1000FG456) FPGA. Can you please suggest the pin assignments for the jtag pins of the ORPSoC design? I tried using the jtag pins on the FPGA which are c19(TCK),D3(TDI), D20 (TDO), B20(TMS). But it is giving DRC errors in Xilinx ISE PACE. Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx spartan3 Parallel port JTAG cable which we modified with flying leads to fit to RC200 board to establish the communication. The modified cable works fine with the Xilinx impact and detects the JTAG chain.What implications can this have on my design not working? Really would appreciate any sort of help ASAP........... Thanks in advance for your support... Best Regards Sona _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

ORPSoC JTAG pin assignment by Unknown on Jan 13, 2005			Not available!
Dear sir, Thanks very much for the help. I tried with expansion header pins , similar to the ones in the ucf file uploaded under rc203. I used the fpga general i/o pinouts m2,n2,p2,m4 (TCK,TDI,TDO,TMS) which is connected to the expansion header. I used one of the buttons to trst signal. Iam getting the error message saying reset() "crc failed" Will it be my communication problem or some problem in my design? Thanks and best regards Sona ----- Original Message ----- From: jcastillo<<A HREF="mailto:jcastillo@o...">jcastillo@o...</A>> To: Date: Thu Jan 13 12:08:02 CET 2005 Subject: [openrisc] ORPSoC JTAG pin assignment [q]>Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx [/q] spartan3 [q]>Parallel port JTAG cable which we modified with flying leads to [/q] fit to [q]>RC200 board to establish the communication. The modified cable [/q] works [q]>fine with the Xilinx impact and detects the JTAG chain.What [/q] implications [q]>can this have on my design not working? >Really would appreciate any sort of help ASAP........... >Thanks in advance for your support... >Best Regards >Sona [/q] The ucf files are prepared to connect the parallel cable to the expansion header, take a look to it to see how to connect them. To program the FPGA use the FTU program provided by Celoxica or [/q] use [q] another JTAG cable connected to the JTAG header to program the FPGA. Best Regards Javier Castillo <A HREF="mailto:jcastillo@o...">jcastillo@o...</A> _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> [/q] Dear sir, Thanks very much for the help. I tried with expansion header pins , similar to the ones in the ucf file uploaded under rc203. I used the fpga general i/o pinouts m2,n2,p2,m4 (TCK,TDI,TDO,TMS) which is connected to the expansion header. I used one of the buttons to trst signal. Iam getting the error message saying reset() "crc failed" Will it be my communication problem or some problem in my design? Thanks and best regards Sona ----- Original Message ----- From: jcastillojcastillo@o...> To: Date: Thu Jan 13 12:08:02 CET 2005 Subject: [openrisc] ORPSoC JTAG pin assignment >Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx spartan3 >Parallel port JTAG cable which we modified with flying leads to fit to >RC200 board to establish the communication. The modified cable works >fine with the Xilinx impact and detects the JTAG chain.What implications >can this have on my design not working? >Really would appreciate any sort of help ASAP........... >Thanks in advance for your support... >Best Regards >Sona The ucf files are prepared to connect the parallel cable to the expansion header, take a look to it to see how to connect them. To program the FPGA use the FTU program provided by Celoxica or use another JTAG cable connected to the JTAG header to program the FPGA. Best Regards Javier Castillo jcastillo@o... _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

ORPSoC JTAG pin assignment by Unknown on Jan 17, 2005			Not available!
Usually that's the problem with the communication although it could also be the bad RTL (the way you connected signals). Regards, Igor On Thu, 13 Jan 2005 15:55:44 +0100, <A HREF="mailto:somatomy@yahoo.com">somatomy@yahoo.com</A> <<A HREF="mailto:somatomy@yahoo.com">somatomy@yahoo.com</A>> wrote: [q] Dear sir, Thanks very much for the help. I tried with expansion header pins , similar to the ones in the ucf file uploaded under rc203. I used the fpga general i/o pinouts m2,n2,p2,m4 (TCK,TDI,TDO,TMS) which is connected to the expansion header. I used one of the buttons to trst signal. Iam getting the error message saying reset() "crc failed" Will it be my communication problem or some problem in my design? Thanks and best regards Sona ----- Original Message ----- From: jcastillo<<A HREF="mailto:jcastillo@o...">jcastillo@o...</A>> To: Date: Thu Jan 13 12:08:02 CET 2005 Subject: [openrisc] ORPSoC JTAG pin assignment [q] >Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx[/q] > spartan3 [q] >Parallel port JTAG cable which we modified with flying leads to[/q] > fit to [q] >RC200 board to establish the communication. The modified cable[/q] > works [q] >fine with the Xilinx impact and detects the JTAG chain.What[/q] > implications [q] >can this have on my design not working? >Really would appreciate any sort of help ASAP........... >Thanks in advance for your support... >Best Regards >Sona [/q] > The ucf files are prepared to connect the parallel cable to the > expansion > header, take a look to it to see how to connect them. > To program the FPGA use the FTU program provided by Celoxica or[/q] use [q]> another > JTAG cable connected to the JTAG header to program the FPGA. > Best Regards > Javier Castillo > <A HREF="mailto:jcastillo@o...">jcastillo@o...</A> > _______________________________________________ > <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> > > [/q] _______________________________________________ <A HREF="http://www.opencores.org/mailman/listinfo/openrisc">http://www.opencores.org/mailman/listinfo/openrisc</A> [/q] Usually that's the problem with the communication although it could also be the bad RTL (the way you connected signals). Regards, Igor On Thu, 13 Jan 2005 15:55:44 +0100, somatomy@yahoo.com somatomy@yahoo.com> wrote: Dear sir, Thanks very much for the help. I tried with expansion header pins , similar to the ones in the ucf file uploaded under rc203. I used the fpga general i/o pinouts m2,n2,p2,m4 (TCK,TDI,TDO,TMS) which is connected to the expansion header. I used one of the buttons to trst signal. Iam getting the error message saying reset() "crc failed" Will it be my communication problem or some problem in my design? Thanks and best regards Sona ----- Original Message ----- From: jcastillojcastillo@o...> To: Date: Thu Jan 13 12:08:02 CET 2005 Subject: [openrisc] ORPSoC JTAG pin assignment >Secondly, Iam using RC200 Celoxica board. Iam using a Xilinx > spartan3 >Parallel port JTAG cable which we modified with flying leads to > fit to >RC200 board to establish the communication. The modified cable > works >fine with the Xilinx impact and detects the JTAG chain.What > implications >can this have on my design not working? >Really would appreciate any sort of help ASAP........... >Thanks in advance for your support... >Best Regards >Sona > The ucf files are prepared to connect the parallel cable to the > expansion > header, take a look to it to see how to connect them. > To program the FPGA use the FTU program provided by Celoxica or use > another > JTAG cable connected to the JTAG header to program the FPGA. > Best Regards > Javier Castillo > jcastillo@o... > _______________________________________________ > http://www.opencores.org/mailman/listinfo/openrisc > > _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

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