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Whisbone cycle in openrisc core
by Unknown on Jan 30, 2005 |
Not available! | ||
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Hi,
According to the specifications there can be any number of wait states in a whisbone read/write cycle. But when I simulate the openrisc core it seem to fail if there are more that two clock cycles. I get an X driving the cyc_i and std_i if the ack_o is set later that two clock cycles after cyc_i is set. The problem is that i need a cycle longer that that. Any ideas? /Patrik |
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Whisbone cycle in openrisc core
by Unknown on Feb 3, 2005 |
Not available! | ||
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As I understand it is possible to assert err_o to get a retry cycle. But its
not working. Any suggestions how to get longer cycles?
/Patrik
----- Original Message -----
From: patrik.thalin@s...patrik.thalin@s...>
To:
Date: Sun Jan 30 14:27:17 CET 2005
Subject: [openrisc] Whisbone cycle in openrisc core
Hi,
According to the specifications there can be any number of wait states in a whisbone read/write cycle. But when I simulate the openrisc core it seem to fail if there are more that two clock cycles. I get an X driving the cyc_i and std_i if the ack_o is set later that two clock cycles after cyc_i is set. The problem is that i need a cycle longer that that. Any ideas? /Patrik |
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Whisbone cycle in openrisc core
by Unknown on Feb 3, 2005 |
Not available! | ||
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The core should work fine regardless how many wait states you have (assert
of ack to the core after core asserts cyc/stb).
regards,
Damjan
----- Original Message -----
From: patrik.thalin@spdevices.com>
To: openrisc@opencores.org>
Sent: Thursday, February 03, 2005 8:42 PM
Subject: Re: [openrisc] Whisbone cycle in openrisc core
As I understand it is possible to assert err_o to get a retry cycle. But
its
not working. Any suggestions how to get longer cycles?
/Patrik
----- Original Message -----
From: patrik.thalin@s...patrik.thalin@s...>
To:
Date: Sun Jan 30 14:27:17 CET 2005
Subject: [openrisc] Whisbone cycle in openrisc core
Hi,
_______________________________________________
http://www.opencores.org/mailman/listinfo/openrisc
According to the specifications there can be any number of wait states in a whisbone read/write cycle. But when I simulate the openrisc core it seem to fail if there are more that two clock cycles. I get an X driving the cyc_i and std_i if the ack_o is set later that two clock cycles after cyc_i is set. The problem is that i need a cycle longer that that. Any ideas? /Patrik |
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