Dear Helpers: I have successfully designed and downloaded my new processor (cpu.rbf -row binary file format) to an Altera Startix device incorporated in a PCI development board. I have initialized my program memory (PROM) with a small benchmark ( fibo.mif) I have wrote according to the memory initialization file (.mif) format. The program and data memory were also downloaded to the device with teh processor core. I am using Altera Quartus II in my design and I used it to simulate the processor before downloding it to the FPGA devices My question is what's next? I need to simulate my processor and see the contents of the DATA memory and some Registers in the processor that was dowloaded into the FPGA device. Can you please tell me what tool should I use to verify that the processor is running correct with the (fibo.mif) benchmark I have used. Also please tell me is there is any possibility to benefit from the PCI bus. I am thinking to add some debug (signals on the "top" file ) and then use them to read the contents of the DATA memory and registers. But, I do know also how to read those signal without an appropriate tool? Does Quartus II have such capability? Thank so much for your help /Ben UEC, IS, Tokyo -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.opencores.org/forums/openrisc/attachments/20050201/6ed2e22f/attachment.htm