Hi,

Changelog says it all.

ChangeLog:
* Cleanup the memory controller useing the new callbacks.

nog.
-------------- next part --------------
--- peripheral/mc.c 2005-02-05 11:26:06.000000000 +0100
+++ ../or1ksim-ac/peripheral/mc.c 2005-02-05 15:58:54.000000000 +0100
@@ -45,14 +45,12 @@

extern struct dev_memarea *dev_list;

-static struct mc mc;
-
-void set_csc_tms (int cs, unsigned long csc, unsigned long tms) {
+void set_csc_tms (int cs, unsigned long csc, unsigned long tms, struct mc *mc) {
struct dev_memarea *mem_dev = dev_list;

while (mem_dev) {
if (mem_dev->chip_select == cs) {
- mem_dev->addr_mask = mc.ba_mask + mem_dev->addr_mask = mc->ba_mask mem_dev->addr_compare = ((csc >> MC_CSC_SEL_OFFSET) /* & 0xff*/) mem_dev->valid = (csc >> MC_CSC_EN_OFFSET) & 0x01;

@@ -78,67 +76,69 @@
/* Set a specific MC register with value. */
void mc_write_word(oraddr_t addr, uint32_t value, void *dat)
{
+ struct mc *mc = dat;
int chipsel;

debug(5, "mc_write_word(%"PRIxADDR",%08"PRIx32")\n", addr, value);

- addr -= config.mc.baseaddr;
+ addr -= mc->baseaddr;

switch (addr) {
case MC_CSR:
- mc.csr = value;
+ mc->csr = value;
break;
case MC_POC:
fprintf (stderr, "warning: write to MC's POC register!");
break;
case MC_BA_MASK:
- mc.ba_mask = value & MC_BA_MASK_VALID;
+ mc->ba_mask = value & MC_BA_MASK_VALID;
for (chipsel = 0; chipsel - set_csc_tms (chipsel, mc.csc[chipsel], mc.tms[chipsel]);
+ set_csc_tms (chipsel, mc->csc[chipsel], mc->tms[chipsel], mc);
break;
default:
if (addr >= MC_CSC(0) && addr addr -= MC_CSC(0);
if ((addr >> 2) & 1)
- mc.tms[addr >> 3] = value;
+ mc->tms[addr >> 3] = value;
else
- mc.csc[addr >> 3] = value;
+ mc->csc[addr >> 3] = value;

- set_csc_tms (addr >> 3, mc.csc[addr >> 3], mc.tms[addr >> 3]);
+ set_csc_tms (addr >> 3, mc->csc[addr >> 3], mc->tms[addr >> 3], mc);
break;
} else
- debug(1, "write out of range (addr %"PRIxADDR")\n", addr + config.mc.baseaddr);
+ debug(1, "write out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
}
}

/* Read a specific MC register. */
uint32_t mc_read_word(oraddr_t addr, void *dat)
{
+ struct mc *mc = dat;
uint32_t value = 0;

debug(5, "mc_read_word(%"PRIxADDR")", addr);

- addr -= config.mc.baseaddr;
+ addr -= mc->baseaddr;

switch (addr) {
case MC_CSR:
- value = mc.csr;
+ value = mc->csr;
break;
case MC_POC:
- value = mc.poc;
+ value = mc->poc;
break;
case MC_BA_MASK:
- value = mc.ba_mask;
+ value = mc->ba_mask;
break;
default:
if (addr >= MC_CSC(0) && addr addr -= MC_CSC(0);
if ((addr >> 2) & 1)
- value = mc.tms[addr >> 3];
+ value = mc->tms[addr >> 3];
else
- value = mc.csc[addr >> 3];
+ value = mc->csc[addr >> 3];
} else
- debug(1, " read out of range (addr %"PRIxADDR")\n", addr + config.mc.baseaddr);
+ debug(1, " read out of range (addr %"PRIxADDR")\n", addr + mc->baseaddr);
break;
}
debug(5, " value(%"PRIx32")\n", value);
@@ -146,78 +146,103 @@
}

/* Read POC register and init memory controler regs. */
-void mc_reset()
+void mc_reset(void *dat)
{
+ struct mc *mc = dat;
struct dev_memarea *mem_dev = dev_list;

- if (config.mc.enabled) {
- PRINTF("Resetting memory controller.\n");
- memset(&mc, 0, sizeof(struct mc));
-
- mc.poc = config.mc.POC;
-
- /* Set CS0 */
- mc.csc[0] = (((config.mc.POC & 0x0c) >> 2) -
- if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
- mc.tms[0] = MC_TMS_ASYNC_VALID;
- } else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
- mc.tms[0] = MC_TMS_SDRAM_VALID;
- } else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
- mc.tms[0] = MC_TMS_SSRAM_VALID;
- } else if ((mc.csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
- mc.tms[0] = MC_TMS_SYNC_VALID;
- }
+ PRINTF("Resetting memory controller.\n");

- while (mem_dev) {
- mem_dev->valid = 0;
- mem_dev = mem_dev->next;
- }
+ memset(mc->csc, 0, sizeof(mc->csc));
+ memset(mc->tms, 0, sizeof(mc->tms));

- set_csc_tms (0, mc.csc[0], mc.tms[0]);
+ mc->csr = 0;
+ mc->ba_mask = 0;

- register_memoryarea(config.mc.baseaddr, MC_ADDR_SPACE, 4, 1, mc_read_word, mc_write_word, NULL);
+ /* Set CS0 */
+ mc->csc[0] = (((mc->poc & 0x0c) >> 2) poc & 0x03) +
+ if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_ASYNC) {
+ mc->tms[0] = MC_TMS_ASYNC_VALID;
+ } else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SDRAM) {
+ mc->tms[0] = MC_TMS_SDRAM_VALID;
+ } else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SSRAM) {
+ mc->tms[0] = MC_TMS_SSRAM_VALID;
+ } else if ((mc->csc[0] >> MC_CSC_MEMTYPE_OFFSET) && 0x07 == MC_CSC_MEMTYPE_SYNC) {
+ mc->tms[0] = MC_TMS_SYNC_VALID;
}
-}

-inline void mc_clock()
-{
+ while (mem_dev) {
+ mem_dev->valid = 0;
+ mem_dev = mem_dev->next;
+ }
+
+ set_csc_tms (0, mc->csc[0], mc->tms[0], mc);
}

-void mc_status()
+void mc_status(void *dat)
{
+ struct mc *mc = dat;
int i;

- PRINTF( "\nMemory Controller at 0x%lX:\n", config.mc.baseaddr );
- PRINTF( "POC: 0x%08lX\n", mc.poc );
- PRINTF( "BAS: 0x%08lX\n", mc.ba_mask );
- PRINTF( "CSR: 0x%08lX\n", mc.csr );
+ PRINTF( "\nMemory Controller at 0x%"PRIxADDR":\n", mc->baseaddr );
+ PRINTF( "POC: 0x%08lX\n", mc->poc );
+ PRINTF( "BAS: 0x%08lX\n", mc->ba_mask );
+ PRINTF( "CSR: 0x%08lX\n", mc->csr );

for (i=0; i- PRINTF( "CE %02d - CSC: 0x%08lX TMS: 0x%08lX\n", i, mc.csc,
- mc.tms);
+ PRINTF( "CE %02d - CSC: 0x%08lX TMS: 0x%08lX\n", i, mc->csc,
+ mc->tms);
}
}

/*-----------------------------------------------------[ MC configuration }---*/
void mc_enabled(union param_val val, void *dat)
{
- config.mc.enabled = val.int_val;
+ struct mc *mc = dat;
+ mc->enabled = val.int_val;
}

void mc_baseaddr(union param_val val, void *dat)
{
- config.mc.baseaddr = val.addr_val;
+ struct mc *mc = dat;
+ mc->baseaddr = val.addr_val;
}

void mc_POC(union param_val val, void *dat)
{
- config.mc.POC = val.int_val;
+ struct mc *mc = dat;
+ mc->poc = val.int_val;
+}
+
+void *mc_sec_start(void)
+{
+ struct mc *new = malloc(sizeof(struct mc));
+
+ if(!new) {
+ fprintf(stderr, "Peripheral MC: Run out of memory\n");
+ exit(-1);
+ }
+
+ new->enabled = 0;
+
+ return new;
+}
+
+void mc_sec_end(void *dat)
+{
+ struct mc *mc = dat;
+
+ if(mc->enabled) {
+ register_memoryarea(mc->baseaddr, MC_ADDR_SPACE, 4, 1, mc_read_word, mc_write_word, dat);
+ reg_sim_reset(mc_reset, dat);
+ reg_sim_stat(mc_status, dat);
+ }
}

void reg_mc_sec(void)
{
- struct config_section *sec = reg_config_sec("mc", NULL, NULL);
+ struct config_section *sec = reg_config_sec("mc", mc_sec_start, mc_sec_end);

reg_config_param(sec, "enabled", paramt_int, mc_enabled);
reg_config_param(sec, "baseaddr", paramt_addr, mc_baseaddr);
--- peripheral/mc.h 2002-09-16 22:48:42.000000000 +0200
+++ ../or1ksim-ac/peripheral/mc.h 2005-02-05 15:52:35.000000000 +0100
@@ -22,10 +22,6 @@
#ifndef __MC_H
#define __MC_H

-void mc_reset();
-void mc_status();
-inline void mc_clock();
-
#define N_CE (8)

#define MC_CSR (0x00)
@@ -118,6 +114,8 @@
unsigned long ba_mask;
unsigned long csc[N_CE];
unsigned long tms[N_CE];
+ oraddr_t baseaddr;
+ int enabled;
};

#endif
--- toplevel.c 2005-02-05 15:55:00.000000000 +0100
+++ ../or1ksim-ac/toplevel.c 2005-02-05 15:55:33.000000000 +0100
@@ -54,7 +54,6 @@
#include "sched.h"
#include "profiler.h"
#include "mprofiler.h"
-#include "mc.h"
#include "gpio.h"
#include "pm.h"
#include "pic.h"
@@ -170,7 +169,6 @@
tick_reset();
pm_reset();
pic_reset();
- mc_reset();
du_reset ();
cpu_reset();
}
--- sim-config.h 2005-02-05 15:55:00.000000000 +0100
+++ ../or1ksim-ac/sim-config.h 2005-02-05 15:56:02.000000000 +0100
@@ -48,12 +48,6 @@
} gpios[MAX_GPIOS];

struct {
- int enabled; /* is MC enabled? */
- unsigned long baseaddr; /* Naturally aligned base address */
- unsigned POC; /* power on reset configuration register */
- } mc;
-
- struct {
int pattern; /* A user specified memory initialization pattern */
int random_seed; /* Initialize the memory with random values, starting with seed */
enum {
--- sim-config.c 2005-02-05 15:55:00.000000000 +0100
+++ ../or1ksim-ac/sim-config.c 2005-02-05 15:55:53.000000000 +0100
@@ -121,9 +123,6 @@
config.dc.store_hitdelay = 0;
config.dc.store_missdelay = 0;

- /* Memory Controller */
- config.mc.enabled = 0;
-
/* CPU */
config.cpu.superscalar = 0;
config.sim.history = 0;
@@ -901,7 +905,6 @@
}
fprintf (f, "},\n");

- fprintf (f, " mc:{enabled:%i, baseaddr:0x%08lx, POC:%i},\n", config.mc.enabled, config.mc.baseaddr, config.mc.POC);
fprintf (f, " memory:{pattern:%i, random_seed:%i, type:%s, nmemories:%i, table:{", config.memory.pattern, config.memory.random_seed,
config.memory.type == MT_UNKNOWN ? "MT_UNKNOWN" : config.memory.type == MT_PATTERN ? "MT_PATTERN" : "MT_RANDOM", config.memory.nmemories);
comma = 0;
--- sim-cmd.c 2005-02-05 15:55:00.000000000 +0100
+++ ../or1ksim-ac/sim-cmd.c 2005-02-05 15:56:14.000000000 +0100
@@ -56,7 +56,6 @@
#include "sprs.h"
#include "immu.h"
#include "dmmu.h"
-#include "mc.h"
#include "icache_model.h"
#include "dcache_model.h"
#include "branch_predict.h"
@@ -419,7 +428,6 @@
if (config.bpb.enabled) bpb_info();
if (config.bpb.btic) btic_info();

- if (config.mc.enabled) mc_status();
if (config.ngpios) gpio_status();

while(cur_stat) {