First level first-level exception handlers can only use relative to r0 addressing, It is a limit on one processor and a problem on SMP environment since each CPU need to have it own information. I suggest to add two System SPR registers, with R/W access in SM mode to help the software. EGPR0 = Exception General Purpuse Register 0 EGPR1 = Exception General Purpuse Register 1 First level exception would look like this: set the first-level exception Stack Pointer (after reset): l.movhi r1,hi(first_level_exception_stack) l.ori r1,lo(first_level_exception_stack) l.mtspr r0,r1,OR1200_SPR_EGPR1 Put CPU information structure on the stack: l.sw r3,(CI_INFO)r1 /* Store CPU Infomation pointer to stack*/ Dispatch first-level exception: l.mtspr r0, r1,OR1200_SPR_EGPR0 /* Save Stack Pointer to EGPR0 */ l.mfspr r1, r0,OR1200_SPR_EGPR1 /* Load Exception Stack Pointer from EGPR1*/ l.sw (GPR2)r1, r2 /* Save Frame Pointer*/ l.mfspr r2,r0,OR1200_SPR_EGPR0 /* Load previous Stack Pointer from EGPR0 */ l.sw (GPR1)r1,r2 /* Save previous Stack Pointer */ l.add r2,r1,new_frame_value_reteleve_to_stack_pointer /* Calculate new frame */ l.sw (GPR3)r1,r3 . l.sw (GPR4)r1,r4 . . . l.sw (GPR31)r1,r31 Get CPU information structure: l.lwz (CI_INFO)r1,r3 /* Load CPU Infomation pointer from stack*/ This suggestion is inspired from powerpc : "SPRG0-SPRG3 - Only the 600 family has these general-purpose SPR registers, which the program can use as needed. Conventionally, for the 600 family processors SPRG0 is reserved as register containing the value for a stack pointer to be used by the first-level exception handler. SPRG1 is then used in first-level exception handlers to save a GPR, which is then used as a stack pointer for saving other registers by copying the content of SPRG0 to the saved GPR. The EABI specifies that GPR1 is used as the stack pointer and is always valid, so saving it using by means of an SPRG, or any other method, is not necessary when running EABI compliant programs. " http://www.xtrj.org/ppc/ppc2.htm Best Regards. Nir Mor.