Hi all,
I want to use the OR1200 with instruction cache. So I commented the
OR1200_NO_IC in the defines file and uncommented the OR1200_IC_1W_8KB
defines. But still 'ic_en' signal was not getting enabled. If I try to
enable it by hardwiring the assigning of ic_en then it starts reading
garbage (all 'x' s) from the cache and causes abnormal function. So
what is the correct way to enable instruction cache?

Thanks,
Sankar

You have to write in the SR the bits which enables the cache operation. This operation has to be done by the software. Regards Javier Castillo jcastillo@opensocdesign.com -----Mensaje original----- De: openrisc-bounces@opencores.org [mailto:openrisc-bounces@opencores.org] En nombre de sankar@mail.cerc.utexas.edu Enviado el: sábado, 12 de febrero de 2005 0:54 Para: openrisc@opencores.org Asunto: [openrisc] instruction cache Hi all, I want to use the OR1200 with instruction cache. So I commented the OR1200_NO_IC in the defines file and uncommented the OR1200_IC_1W_8KB defines. But still 'ic_en' signal was not getting enabled. If I try to enable it by hardwiring the assigning of ic_en then it starts reading garbage (all 'x' s) from the cache and causes abnormal function. So what is the correct way to enable instruction cache? Thanks, Sankar _______________________________________________ http://www.opencores.org/mailman/listinfo/openrisc

* jcastillo (jcastillo@opensocdesign.com) wrote: Also, don't forget to clear the cache before you enable it... best regards, p.

Hello, Could you give a software example (preferrably in assembly) which does that? I am asking this because I thought while using or32-uclinux tools to compile my assembly with cache that is automatically done. I have included the Makefile below. ************************************* all: test-icdc test-icdc: test.o ../support/reset-icdc.o or32-uclinux-ld -T ../support/orp.ld $? -o $@.or32 ./support/libsupport.a or32-uclinux-objcopy -O binary $@.or32 $@.bin ../utils/bin2hex $@.bin > $@.hex cp $@.hex ../../sim/src/ test.o: test.S or32-uclinux-gcc -O0 $? -c -o $@ clean: rm -f *.o *.or32 *.log *.bin *.hex ****************************************** Could you tell me what the problem is? Thanks, Sankar ----- Original Message ----- From: Matjaz Breskvarphoenix@o...> To: Date: Wed Feb 16 01:36:52 CET 2005 Subject: [openrisc] instruction cache

* sankar@mail.cerc.utexas.edu (sankar@mail.cerc.utexas.edu) wrote: Hi,

This is from Linux...

The define names may or may not be obvious to you... if
they are not please ask again... ;)


# define ENTRY(symbol) \
.global symbol ;\
symbol:


ENTRY(_ic_enable)
SF_DISABLED(r6,INIT_IC_ADDR)
l.bf 9f
l.nop

/* Disable IC */
l.mfspr r6,r0,SPR_SR
l.addi r5,r0,-1
l.xori r5,r5,SPR_SR_ICE
l.and r5,r6,r5
l.mtspr r0,r5,SPR_SR

/* Invalidate IC */
l.addi r6,r0,0
l.addi r5,r0,IC_SIZE
1:
l.mtspr r0,r6,SPR_ICBIR
l.sfne r6,r5
l.bf 1b
l.addi r6,r6,IC_LINE

/* Enable IC */
l.mfspr r6,r0,SPR_SR
l.ori r6,r6,SPR_SR_ICE
l.mtspr r0,r6,SPR_SR
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
l.nop
9:
l.jr r9
l.nop


ENTRY(_dc_enable)
SF_DISABLED(r6,INIT_DC_ADDR)
l.bf 9f
l.nop

/* Disable DC */
l.mfspr r6,r0,SPR_SR
l.addi r5,r0,-1
l.xori r5,r5,SPR_SR_DCE
l.and r5,r6,r5
l.mtspr r0,r5,SPR_SR

/* Flush DC */
l.addi r6,r0,0
l.addi r5,r0,DC_SIZE
1:
l.mtspr r0,r6,SPR_DCBIR
l.sfne r6,r5
l.bf 1b
l.addi r6,r6,DC_LINE

/* Enable DC */
l.mfspr r6,r0,SPR_SR
l.ori r6,r6,SPR_SR_DCE
l.mtspr r0,r6,SPR_SR
9:
l.jr r9
l.nop




or32-uclinux tools do not automaticaly clear the cache. the code
in the source file has to do it explicitly...

best regards,
p.

Ok, i should have removed some code from this two functions. it's commented out in this email... best regards, p. * Matjaz Breskvar (phoenix@opencores.org) wrote:
/*
* SF_DISABLED(r6,INIT_IC_ADDR)
* l.bf 9f
* l.nop
*/

/*
* SF_DISABLED(r6,INIT_DC_ADDR)
* l.bf 9f
* l.nop
*/