Hi everyone

I am new to opencores. I am interested in Soc design and tried to
synthesize a openrisc 1200 SOC for my SPARTAN XILINX S1000 FPGA.

However my SOC with ethernet, debug, sram if, flash if and CPU says:

Selected Device : 3s1000ft256-5

Number of Slices: 9344 out of 7680 121% (*)
Number of Slice Flip Flops: 5659 out of 15360 36%
Number of 4 input LUTs: 17410 out of 15360 113% (*)
Number of bonded IOBs: 148 out of 173 85%
Number of BRAMs: 7 out of 24 29%
Number of MULT18X18s: 4 out of 24 16%
Number of GCLKs: 3 out of 8 37%

Do I just need another (bigger) FPGA? Any comments?

Thx for any hints

Regards

Dom

Dominic Buchstaller schrieb:


Yes, you do, I don't think there is a realistic chance to get it smaller.

Look at all the *defines.v files, there are options that affect the size. regards, Damjan ----- Original Message ----- From: "Dominic Buchstaller" dbuchstaller@web.de> To: openrisc@opencores.org> Sent: Thursday, March 10, 2005 7:20 PM Subject: [openrisc] FPGA sice

On Thursday 10 March 2005 20:20, Dominic Buchstaller wrote:


On what board exactly try to build ?



Try disable ethernet part otherwise will not fit. Or try to cut down from
or1200 by customizing its cache size or other things.

If you use XSA-3S1000 board there I have a ready made working project
if interested in it.

Hi again I got the XESS XSA3S-1000 (http://www.xess.com/prod035.php3) I am absolutely interested in other projects - mainly to learn how to build and configure SOC systems. Any links? Thx for the tip with the cach - 'll try that Regards Dom

Hi

Wow - did't think that it would be that much (still with ethernet, sram
if, flash if and vga - what I forgot to mension in my last post):

Selected Device : 3s1000ft256-5

Number of Slices: 5518 out of 7680 71%
Number of Slice Flip Flops: 5257 out of 15360 34%
Number of 4 input LUTs: 9901 out of 15360 64%
Number of bonded IOBs: 148 out of 173 85%
Number of BRAMs: 7 out of 24 29%
Number of MULT18X18s: 4 out of 24 16%
Number of GCLKs: 3 out of 8 37%

I commeted the following in or1200_defines.v out:

`define OR1200_PM_IMPLEMENTED
`define OR1200_DU_IMPLEMENTED
`define OR1200_QMEM_IMPLEMENTED

and set caches to

`define OR1200_IC_1W_512B
//`define OR1200_IC_1W_4KB
//`define OR1200_IC_1W_8KB
`define OR1200_DC_1W_4KB

Ok - so far.

Next question is how do I connect my or1200's FLASH interface with 8bit
width to my 16bit FLASH (CPLD?). And can or1200 drive SDRAM directly or do
I have to use the CPLD to make the SDRAM look like SRAM?

Thanks in advance for any help

Regards

Dom