We are currently working on running SPEC CPU 2006 Benchmarks and MediaBench I benchmarks on OR1200 Core. We are facing some issues during the cross compilation stage using the or32-uclinux-gcc and or32-uclinux-ld commands. We are able to generate the .or32 executable using the above two commands. We could get this done only when we explicitly linked the libgcc.a and libc.a libraries together with the .o object file using the or32-uclinux-ld command. We then use this .or32 to run the architectural simulator or1ksim for generating the execution trace.

The issue we are currently facing is that whenever standard 'C' functions (like fopen(), atoi()) are encountered in the main() function of the benchmark executable, the architectural simulator (or1ksim) or32-uclinux-sim doesn't seem to figure out how to go about executing this function and it just hangs ending up in an infinite loop. The execution gets hanged at this stage and no new functions are executed in the main. For example : if fopen() is encountered, the architectural simulator calls a function __stdio_fopen. It doesn't seem to exit out of this command. I am attaching a log file which shows this problem. Same is the case for atoi() as well.

Are we missing something important? Or do we need to link additional libraries explicitly during linking stage. Currently, i pick up the libc.a from this path (/opt/or32/lib/libc.a) and libgcc.a library from this( /opt/or32/lib/gcc/or32-uclinux/3.4.4/libgcc.a).
Here are the commands i use for generating the .or32 executable. THe below commands are for compiling Mediabench I "g721 encode" Benchmark. Here are the makefile commands.

or32-uclinux-gcc encode.c g711.c g72x.c g721.c g723_24.c g723_40.c -o g721_encode.o
or32-uclinux-ld -T ../sw/support/orp.ld g721_encode.c ../sw/support/reset-nocache.o ../sw/support/libsupport.a /opt/or32/lib/libc.a /opt/or32/lib/gcc/or32-uclinux/3.4.4/libgcc.a -o g721_encode.or32

Has anyone compiled SPEC CPU 2006 benchmarks for OR1200 before? Are there any cross compiled binaries readily available for SPEC CPU2006 benchmarks or MediaBench I benchmarks, which we can directly used in our RTL simulation environment? Please let us know.

Waiting for a reply,

Thanks,
Vinayak & Swapnil

Attached is the log file....

Attaching the log file... Check the instructions at the end : l.j 0x0. At this point, it goes into an infinite loop.


_reset:
r1 =00014840 r1 =00014840 040020d4 l.addi r1,r1,-8
EA =00014844 PA =00014844 r2 =040020d4 040020d8 l.sw 0x4(r1),r2
r2 =00014848 r1 =00014840 040020dc l.addi r2,r1,0x8
EA =00014840 PA =00014840 r9 =0400abb0 040020e0 l.sw 0x0(r1),r9
040020e4 l.jal -1956
040020e8 l.nop 0
_main:
r1 =0001477c r1 =0001477c 04000254 l.addi r1,r1,-196
EA =00014788 PA =00014788 r2 =00014848 04000258 l.sw 0xc(r1),r2
r2 =00014840 r1 =0001477c 0400025c l.addi r2,r1,0xc4
EA =00014784 PA =00014784 r9 =040020ec 04000260 l.sw 0x8(r1),r9
EA =0001478c PA =0001478c r10=00000000 04000264 l.sw 0x10(r1),r10
EA =00014790 PA =00014790 r12=00000000 04000268 l.sw 0x14(r1),r12
EA =00014794 PA =00014794 r14=00000000 0400026c l.sw 0x18(r1),r14
EA =00014798 PA =00014798 r16=00000000 04000270 l.sw 0x1c(r1),r16
EA =0001479c PA =0001479c r18=00000000 04000274 l.sw 0x20(r1),r18
EA =000147a0 PA =000147a0 r20=00000000 04000278 l.sw 0x24(r1),r20
EA =000147a4 PA =000147a4 r22=00000000 0400027c l.sw 0x28(r1),r22
EA =000147a8 PA =000147a8 r24=00000000 04000280 l.sw 0x2c(r1),r24
EA =000147ac PA =000147ac r26=00000000 04000284 l.sw 0x30(r1),r26
EA =000147b0 PA =000147b0 r28=00000000 04000288 l.sw 0x34(r1),r28
EA =000147b4 PA =000147b4 r30=00000000 0400028c l.sw 0x38(r1),r30
r14=00000000 r3 =00000000 04000290 l.ori r14,r3,0
r30=0001480c r2 =00014840 04000294 l.addi r30,r2,-52
r10=00000000 r4 =00000000 04000298 l.ori r10,r4,0
r22=01000000 0400029c l.movhi r22,0x100
r22=0100d738 r22=0100d738 040002a0 l.ori r22,r22,0xd738
040002a4 l.jal 0x226
r3 =0001480c r30=0001480c 040002a8 l.ori r3,r30,0
_g72x_init_state:
r1 =00014778 r1 =00014778 04000b3c l.addi r1,r1,-4
EA =00014778 PA =00014778 r2 =00014840 04000b40 l.sw 0x0(r1),r2
r2 =0001477c r1 =00014778 04000b44 l.addi r2,r1,0x4
r4 =00008800 04000b48 l.ori r4,r0,0x8800
r5 =00000000 04000b4c l.addi r5,r0,0x0
EA =0001480c PA =0001480c r4 =00008800 04000b50 l.sw 0x0(r3),r4
EA =00014812 PA =00014812 r5 =00000000 04000b54 l.sh 0x6(r3),r5
r4 =00000220 04000b58 l.addi r4,r0,0x220
EA =00014814 PA =00014814 r5 =00000000 04000b5c l.sh 0x8(r3),r5
EA =00014810 PA =00014810 r4 =00000220 04000b60 l.sh 0x4(r3),r4
EA =00014816 PA =00014816 r5 =00000000 04000b64 l.sh 0xa(r3),r5
r4 =00000000 r5 =00000000 r5 =00000000 04000b68 l.add r4,r5,r5
r6 =00000020 04000b6c l.addi r6,r0,0x20
r4 =0001480c r4 =0001480c r3 =0001480c 04000b70 l.add r4,r4,r3
r5 =00000001 r5 =00000001 04000b74 l.addi r5,r5,0x1
EA =00014838 PA =00014838 r6 =00000020 04000b78 l.sh 0x2c(r4),r6
r5 =00000001 04000b7c l.sfgtsi r5,0x1
--------------------- 2000 instruction ---------------------
r6 =00000000 04000b80 l.addi r6,r0,0x0
EA =00014818 PA =00014818 r6 =00000000 04000b84 l.sh 0xc(r4),r6
SR =00008001 04000b88 l.bnf -8
EA =00014828 PA =00014828 r6 =00000000 04000b8c l.sh 0x1c(r4),r6
r4 =00000002 r5 =00000001 r5 =00000001 04000b68 l.add r4,r5,r5
r6 =00000020 04000b6c l.addi r6,r0,0x20
r4 =0001480e r4 =0001480e r3 =0001480c 04000b70 l.add r4,r4,r3
r5 =00000002 r5 =00000002 04000b74 l.addi r5,r5,0x1
EA =0001483a PA =0001483a r6 =00000020 04000b78 l.sh 0x2c(r4),r6
r5 =00000002 04000b7c l.sfgtsi r5,0x1
r6 =00000000 04000b80 l.addi r6,r0,0x0
EA =0001481a PA =0001481a r6 =00000000 04000b84 l.sh 0xc(r4),r6
SR =00008201 04000b88 l.bnf -8
EA =0001482a PA =0001482a r6 =00000000 04000b8c l.sh 0x1c(r4),r6
r5 =00000000 04000b90 l.addi r5,r0,0x0
r4 =00000000 r5 =00000000 r5 =00000000 04000b94 l.add r4,r5,r5
r6 =00000020 04000b98 l.addi r6,r0,0x20
r4 =0001480c r4 =0001480c r3 =0001480c 04000b9c l.add r4,r4,r3
r5 =00000001 r5 =00000001 04000ba0 l.addi r5,r5,0x1
EA =0001482c PA =0001482c r6 =00000020 04000ba4 l.sh 0x20(r4),r6
r5 =00000001 04000ba8 l.sfgtsi r5,0x5
r6 =00000000 04000bac l.addi r6,r0,0x0
SR =00008001 04000bb0 l.bnf -7
EA =0001481c PA =0001481c r6 =00000000 04000bb4 l.sh 0x10(r4),r6
r4 =00000002 r5 =00000001 r5 =00000001 04000b94 l.add r4,r5,r5
r6 =00000020 04000b98 l.addi r6,r0,0x20
r4 =0001480e r4 =0001480e r3 =0001480c 04000b9c l.add r4,r4,r3
r5 =00000002 r5 =00000002 04000ba0 l.addi r5,r5,0x1
EA =0001482e PA =0001482e r6 =00000020 04000ba4 l.sh 0x20(r4),r6
r5 =00000002 04000ba8 l.sfgtsi r5,0x5
r6 =00000000 04000bac l.addi r6,r0,0x0
SR =00008001 04000bb0 l.bnf -7
EA =0001481e PA =0001481e r6 =00000000 04000bb4 l.sh 0x10(r4),r6
r4 =00000004 r5 =00000002 r5 =00000002 04000b94 l.add r4,r5,r5
r6 =00000020 04000b98 l.addi r6,r0,0x20
r4 =00014810 r4 =00014810 r3 =0001480c 04000b9c l.add r4,r4,r3
r5 =00000003 r5 =00000003 04000ba0 l.addi r5,r5,0x1
EA =00014830 PA =00014830 r6 =00000020 04000ba4 l.sh 0x20(r4),r6
r5 =00000003 04000ba8 l.sfgtsi r5,0x5
r6 =00000000 04000bac l.addi r6,r0,0x0
SR =00008001 04000bb0 l.bnf -7
EA =00014820 PA =00014820 r6 =00000000 04000bb4 l.sh 0x10(r4),r6
r4 =00000006 r5 =00000003 r5 =00000003 04000b94 l.add r4,r5,r5
r6 =00000020 04000b98 l.addi r6,r0,0x20
r4 =00014812 r4 =00014812 r3 =0001480c 04000b9c l.add r4,r4,r3
r5 =00000004 r5 =00000004 04000ba0 l.addi r5,r5,0x1
EA =00014832 PA =00014832 r6 =00000020 04000ba4 l.sh 0x20(r4),r6
r5 =00000004 04000ba8 l.sfgtsi r5,0x5
r6 =00000000 04000bac l.addi r6,r0,0x0
SR =00008001 04000bb0 l.bnf -7
--------------------- 2050 instruction ---------------------
EA =00014822 PA =00014822 r6 =00000000 04000bb4 l.sh 0x10(r4),r6
r4 =00000008 r5 =00000004 r5 =00000004 04000b94 l.add r4,r5,r5
r6 =00000020 04000b98 l.addi r6,r0,0x20
r4 =00014814 r4 =00014814 r3 =0001480c 04000b9c l.add r4,r4,r3
r5 =00000005 r5 =00000005 04000ba0 l.addi r5,r5,0x1
EA =00014834 PA =00014834 r6 =00000020 04000ba4 l.sh 0x20(r4),r6
r5 =00000005 04000ba8 l.sfgtsi r5,0x5
r6 =00000000 04000bac l.addi r6,r0,0x0
SR =00008001 04000bb0 l.bnf -7
EA =00014824 PA =00014824 r6 =00000000 04000bb4 l.sh 0x10(r4),r6
r4 =0000000a r5 =00000005 r5 =00000005 04000b94 l.add r4,r5,r5
r6 =00000020 04000b98 l.addi r6,r0,0x20
r4 =00014816 r4 =00014816 r3 =0001480c 04000b9c l.add r4,r4,r3
r5 =00000006 r5 =00000006 04000ba0 l.addi r5,r5,0x1
EA =00014836 PA =00014836 r6 =00000020 04000ba4 l.sh 0x20(r4),r6
r5 =00000006 04000ba8 l.sfgtsi r5,0x5
r6 =00000000 04000bac l.addi r6,r0,0x0
SR =00008201 04000bb0 l.bnf -7
EA =00014826 PA =00014826 r6 =00000000 04000bb4 l.sh 0x10(r4),r6
r4 =00000000 04000bb8 l.addi r4,r0,0x0
EA =0001483c PA =0001483c r4 =00000000 04000bbc l.sb 0x30(r3),r4
r2 =00000000 EA =00014778 PA =00014778 04000bc0 l.lwz r2,0x0(r1)
r9 =040002ac 04000bc4 l.jr r9
r1 =0001477c r1 =0001477c 04000bc8 l.addi r1,r1,0x4
r3 =01000000 040002ac l.movhi r3,0x100
r3 =0100aa7c r3 =0100aa7c 040002b0 l.ori r3,r3,0xaa7c
r20=ffffffc8 r2 =00000000 040002b4 l.addi r20,r2,-56
r26=01000000 040002b8 l.movhi r26,0x100
r26=010015b0 r26=010015b0 040002bc l.ori r26,r26,0x15b0
040002c0 l.jal 0x791
EA =0001477c PA =0001477c r3 =0100aa7c 040002c4 l.sw 0x0(r1),r3
_printf:
r1 =00014778 r1 =00014778 04002104 l.addi r1,r1,-4
EA =00014778 PA =00014778 r2 =00000000 04002108 l.sw 0x0(r1),r2
r2 =0001477c r1 =00014778 0400210c l.addi r2,r1,0x4
r4 =00000000 EA =0001477c PA =0001477c 04002110 l.lwz r4,0x0(r2)
r3 =00014780 r2 =0001477c 04002114 l.addi r3,r2,0x4
r3 =00000000 r4 =00000000 04002118 l.addi r3,r4,0x0
r4 =00000000 r3 =00000000 0400211c l.addi r4,r3,0x0
SIMPRINTF: 04002120 l.nop 0x3
r2 =00000000 EA =00014778 PA =00014778 04002124 l.lwz r2,0x0(r1)
r9 =040002c8 04002128 l.jr r9
r1 =0001477c r1 =0001477c 0400212c l.addi r1,r1,0x4
r3 =01000000 040002c8 l.movhi r3,0x100
r3 =0100aa81 r3 =0100aa81 040002cc l.ori r3,r3,0xaa81
r4 =01000000 040002d0 l.movhi r4,0x100
r4 =0100aa8b r4 =0100aa8b 040002d4 l.ori r4,r4,0xaa8b
040002d8 l.jal 0x89b
r18=00000004 040002dc l.addi r18,r0,0x4
_fopen:
r1 =00014774 r1 =00014774 04002544 l.addi r1,r1,-8
EA =00014778 PA =00014778 r2 =00000000 04002548 l.sw 0x4(r1),r2
--------------------- 2100 instruction ---------------------
r2 =0001477c r1 =00014774 0400254c l.addi r2,r1,0x8
EA =00014774 PA =00014774 r9 =040002e0 04002550 l.sw 0x0(r1),r9
r5 =00000000 04002554 l.addi r5,r0,0x0
04002558 l.jal 0x2e0
r6 =ffffffff 0400255c l.addi r6,r0,-1
__stdio_fopen:
r1 =00014750 r1 =00014750 040030d8 l.addi r1,r1,-36
EA =0001475c PA =0001475c r2 =0001477c 040030dc l.sw 0xc(r1),r2
r2 =00014774 r1 =00014750 040030e0 l.addi r2,r1,0x24
EA =00014758 PA =00014758 r9 =04002560 040030e4 l.sw 0x8(r1),r9
EA =00014760 PA =00014760 r10=00000000 040030e8 l.sw 0x10(r1),r10
EA =00014764 PA =00014764 r12=00000000 040030ec l.sw 0x14(r1),r12
EA =00014768 PA =00014768 r14=00000000 040030f0 l.sw 0x18(r1),r14
EA =0001476c PA =0001476c r16=00000000 040030f4 l.sw 0x1c(r1),r16
EA =00014770 PA =00014770 r18=00000004 040030f8 l.sw 0x20(r1),r18
r16=0100aa81 r3 =0100aa81 040030fc l.ori r16,r3,0
r10=00000000 r5 =00000000 04003100 l.ori r10,r5,0
r3 =00000000 EA =0100aa8b PA =0100aa8b 04003104 l.lbs r3,0x0(r4)
r18=ffffffff r6 =ffffffff 04003108 l.ori r18,r6,0
r3 =00000000 0400310c l.sfeqi r3,0x72
SR =00008001 04003110 l.bf 0x17
r14=00000000 04003114 l.addi r14,r0,0x0
r3 =00000000 04003118 l.sfeqi r3,0x77
SR =00008001 0400311c l.bf 0x14
r14=00000241 04003120 l.addi r14,r0,0x241
r3 =00000000 04003124 l.sfeqi r3,0x61
SR =00008001 04003128 l.bf 0x11
r14=00000441 0400312c l.addi r14,r0,0x441
r4 =00000016 04003130 l.addi r4,r0,0x16
r3 =01000000 04003134 l.movhi r3,0x100
r3 =0100d718 r3 =0100d718 04003138 l.ori r3,r3,0xd718
r10=00000000 0400313c l.sfeqi r10,0x0
SR =00008201 04003140 l.bf 0x9
EA =0100d718 PA =0100d718 r4 =00000016 04003144 l.sw 0x0(r3),r4
04003164 l.j 0x6a
r11=00000000 04003168 l.addi r11,r0,0x0
r9 =00000000 EA =00014758 PA =00014758 0400330c l.lwz r9,0x8(r1)
r2 =00000000 EA =0001475c PA =0001475c 04003310 l.lwz r2,0xc(r1)
r10=00000000 EA =00014760 PA =00014760 04003314 l.lwz r10,0x10(r1)
r12=00000000 EA =00014764 PA =00014764 04003318 l.lwz r12,0x14(r1)
r14=00000000 EA =00014768 PA =00014768 0400331c l.lwz r14,0x18(r1)
r16=00000000 EA =0001476c PA =0001476c 04003320 l.lwz r16,0x1c(r1)
r18=00000000 EA =00014770 PA =00014770 04003324 l.lwz r18,0x20(r1)
r9 =00000000 04003328 l.jr r9
r1 =00014774 r1 =00014774 0400332c l.addi r1,r1,0x24
_vec_start:
00000000 l.j 0x0
00000004 l.j 0x0
_vec_start:
00000000 l.j 0x0
00000004 l.j 0x0
_vec_start:
00000000 l.j 0x0
00000004 l.j 0x0
--------------------- 2150 instruction ---------------------
_vec_start:
00000000 l.j 0x0
00000004 l.j 0x0
_vec_start:
00000000 l.j 0x0
00000004 l.j 0x0
_vec_start:
00000000 l.j 0x0
00000004 l.j 0x0
_vec_start:
00000000 l.j 0x0
00000004 l.j 0x0

Hi Vinayak & Swapnil,

I think the problem is you are linking using ld, rather than using gcc, and something is going wrong with the C library linkage. Have you tried linking using gcc? That should automatically pull in the C libraries.

I'll be interested in the results when you get it all working?

HTH,

Jeremy

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Have you made any estimates on how long it will take to run CPU2006 on this processor? For a processor like OR1200 I would think that CPU2000 would be more appropriate?

/Jan