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How to sim OR1200 rtl
by chienhsinlin on Sep 7, 2009
chienhsinlin
Posts: 2
Joined: Sep 13, 2004
Last seen: Mar 1, 2023
Hi! All:

I've been trying to run or1200-rel1 rtl simulation under linux. In the sim directory, there is a README file where it said "Simulation scripts for or1200 are available in the opencores cvs under or1k/orp.

Could any one tell me where I can get the scripts for simulations.

Thanks alot

Tony Lin
RE: How to sim OR1200 rtl
by jeremybennett on Sep 7, 2009
jeremybennett
Posts: 815
Joined: May 29, 2008
Last seen: Jun 13, 2019
Hi! All:

I've been trying to run or1200-rel1 rtl simulation under linux. In the sim directory, there is a README file where it said "Simulation scripts for or1200 are available in the opencores cvs under or1k/orp.

Could any one tell me where I can get the scripts for simulations.

Thanks alot

Tony Lin

Hi Tony

Is or1k/trunk/orp/orp_soc/sim/bin/run_rtl_regression what you are looking for?

The scripts for ORPSoCv2 are much better shaken down and work with Icarus Verilog as well, so you may be better looking there. Try openrisc/trunk/orpsocv2/sim/run. That has a Makefile to run the simulations.

HTH

Jeremy

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RE: How to sim OR1200 rtl
by chienhsinlin on Sep 7, 2009
chienhsinlin
Posts: 2
Joined: Sep 13, 2004
Last seen: Mar 1, 2023
Hi! All:

I've been trying to run or1200-rel1 rtl simulation under linux. In the sim directory, there is a README file where it said "Simulation scripts for or1200 are available in the opencores cvs under or1k/orp.

Could any one tell me where I can get the scripts for simulations.

Thanks alot

Tony Lin

Hi Tony

Is or1k/trunk/orp/orp_soc/sim/bin/run_rtl_regression what you are looking for?

The scripts for ORPSoCv2 are much better shaken down and work with Icarus Verilog as well, so you may be better looking there. Try openrisc/trunk/orpsocv2/sim/run. That has a Makefile to run the simulations.

HTH

Jeremy

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Tel: +44 (1590) 610184
Cell: +44 (7970) 676050
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Hi! Jeremy: I don't see the or1k/trunk/orp/orp_soc/sim/bin/run_rtl_regression directory under the web-svn. However, I probably can use the Makefile under openrisc/trunk/orpsocv2/sim/run to run rtl simulation. regards, Tony
RE: How to sim OR1200 rtl
by jeremybennett on Sep 7, 2009
jeremybennett
Posts: 815
Joined: May 29, 2008
Last seen: Jun 13, 2019
Hi! Jeremy: I don't see the or1k/trunk/orp/orp_soc/sim/bin/run_rtl_regression directory under the web-svn. However, I probably can use the Makefile under openrisc/trunk/orpsocv2/sim/run to run rtl simulation. regards, Tony

Hi Tony

I found it here:

http://www.opencores.org/websvn,listing?repname=or1k&path=%2For1k%2Ftrunk%2Forp%2Forp_soc%2Fsim%2Fbin%2F#path_or1k_trunk_orp_orp_soc_sim_bin_.

If you are using ORPSoC v2, I would use the Makefile, rather than "run" directly, since it will set up all the environment variables you may need.

HTH

Jeremy

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RE: How to sim OR1200 rtl
by system2 on Nov 9, 2009
system2
Posts: 11
Joined: Oct 13, 2009
Last seen: Apr 20, 2010
hi
i have the same problem . I want to simulate the openrisc and not the open risc SOC platform.
The simulation of the orp_soc is done well.
But i want to simulate just the OR1200 processor.
How i must procede?
Thanks
RE: How to sim OR1200 rtl
by jt_eaton on Nov 9, 2009
jt_eaton
Posts: 142
Joined: Aug 18, 2008
Last seen: Sep 29, 2018
i have the same problem . I want to simulate the openrisc and not the open risc SOC platform.
The simulation of the orp_soc is done well.
But i want to simulate just the OR1200 processor.
How i must procede?
-------------------------------------------------------

You usually don't simulate a processor by itself. When I get a new processor I will always start off by instantiating it in my testbench with the NOP opcode forced into it's read_data. Then it only takes clock,reset and a few handshaking lines to get the processor up and stepping through it's memory space. That serves as a quick sanity check that you have all the code and it will simulate.

Any real work is going to need a memory subsystem complete with boot code. That is what the risc SOC projects give you along with some I/O. Write some C or assembler code and load it into the sim to see what it will do. It also can synthesize into a real fpga and you can run the same code on the bench.


So you want to use orpsoc_v2 or minsoc as your development environment.


John Eaton


RE: How to sim OR1200 rtl
by jeremybennett on Nov 10, 2009
jeremybennett
Posts: 815
Joined: May 29, 2008
Last seen: Jun 13, 2019

Hi System2

You might want to consider stripping down the ORPSoCv2 or minsoc to remove peripherals from the bus, so you are left with just OR1200 and the memory subsystem. That will give you a faster model (less to simulate, particularly when using Verilator).

I used to do this with the old ORPSoC, and could run good software demos on my laptop. You may want to consider putting in very simple Verilog memory models for added performance. I haven't tried it with OPRSoCv2 or minsoc, but the approach should be the same.

As John Eaton points out, you'll need a bootloader at the reset vector (0x100). For the simplest programs, just set up the stack and frame pointers to a suitable location in memory (clear of the code) and then jump to _main (the address of the main () program in your C). For example here's what I use:

	.file   "start.s"

	.text
	.org	0x100		# The reset routine goes at 0x100

	.global _start
_start:
	l.addi	r1,r0,0x7f00	# Set SP to value 0x7f00
	l.addi	r2,r1,0x0	# FP and SP are the same
	l.mfspr	r3,r0,17	# Get SR value
	l.ori	r3,r3,0x2	# Set TT exception enable bit
	l.jal   _main		# Jump to main routine
	l.mtspr	r0,r3,17	# Enable exceptions (DELAY SLOT)

	.org	0xFFC
	l.nop			# Guarantee the exception vector space
				# does not have general purpose code

You'll be best linking your code without libraries or startup. Specify that the code should be placed at location 0x0 and ensure the boot code is first on the command line. For example if the above boot code is in start.o and the main program in wibble.o (compiled from wibble.c), then link the program with.

or32-elf-ld -nostartfiles -nodefaultlibs -nostdlib -Ttext 0x0 start.o wibble.o -o wibble

This can then be loaded as your program image - for example using GDB.

You'll need more subtlety with your bootloader if you want to load programs linked with the full GCC library (so you can use C library functions), and then you'll need to think how those functions are supported. Julius Baxter has put some suggestions for using newlib for this purpose on the ORPSoC webpages.

HTH

Jeremy

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RE: How to sim OR1200 rtl
by vamsi007 on Nov 22, 2013
vamsi007
Posts: 1
Joined: Feb 27, 2012
Last seen: Sep 15, 2015
Hi Jeremy

So it is necessary for a memory module to be associated to the Openrisc 1200 processor. I also would like to know if after stripping down the Orpsoc, would we be left with wishbone interface to the OpenRisc1200. I intend to pass signals via testbench to perform simple read and write instructions using verilog. Kindly give me some insight on interfacing the open risc 1200 with a custom hardware.
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