Hi All,

I want to synthesize the OpenRISC processor based SoC and try it out on the following boards - Digilent Spartan-3E based Nexys-2 and Xilinx Virtex-4 based ML-403. I find two directories for the rtl code of the SoC - one at or1k/trunk/or1200/rtl/verilog and another at or1k/trunk/orp/orp_soc/rtl/verilog. Can someone please let know what is the difference between the two and which would be easiest rtl code to follow for someone to start working with OpenRISC.
Also, can I use the Xilinx ISE for synthesizing and generating the bitstream.

Thanks and Regards,
Ram

The or1200 code is the CPU only, without debug interface, memory, everything. So the orp directory you found was a SoC for an older board of opencores or some other group. Nowadays there is a orpsocv2, which has been made for the OpenRISC Development Kit of http://www.orsoc.se/.

I am right now going through the test phase of a minimal openrisc SoC implementation, which uses the new adv_debug_sys and onchip FPGA memory. I would be happy to deliver you the code.

You would only have to create ucf files and configure a definition file.

I'd be happy then if you could then offer the ucf files to the project.

You can send me an email: rfajardo@gmail.com

Greetings,
Raul

Hi Ram,

As Raul points out your should be using ORPSoCv2, (which includes the OR1200v2 core). It is also in the SVN tree - look for the openrisc directory, rather than or1k.

HTH,

Jeremy

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Thank you Raul and Jeremy for replying back.
@Raul : I have dropped you a mail asking for the files.

Thanks Again,
Ram

Hi Raul,

Just curious about the FPGA you are using for the minsoc. I found that my FPGA with 1200K gates is a little small for the SoC. I am trying to squeeze it in. Got any idea on how to reduce the gate count for OR1200, apart from removing the caches and MMU from implementation. Or am I missing something elementary ?

Thanks and Regards,
Ram

Hi Ram,

check under minsoc/doc/minsoc.pdf
How To: 7) Examples: b) Spartan 3E Starter Kit:
minsoc_defines.v
comment `define SPARTAN3A
uncomment `define SPARTAN3E
change CLOCK_DIVISOR from 5 to 2
comment `define ETHERNET
or1200_defines.v
uncomment `define OR1200_XILINX_RAMB16

This way I got it into the Spartan3E 500.

It should really be no problem for a 1200k gates FPGA.

But to answer your question, I'm using the Spartan3A 1800 DSP.

Good luck!

Raul

hi
is it really possible to run OpenRisc SoC on Spartan 3e 500 ?
Or i'd better buy DE0 nano ?