OpenCores

OpenCores

minsoc generate_bench

no use

no use

1/1

no use

no use

minsoc generate_bench by jb007 on Sep 17, 2010			jb007 Posts: 29 Joined: May 3, 2009 Last seen: Jun 29, 2020
Hi all, trying to run minsoc on a different system to my desktop. I get the following when I run ./generate_bench. Any ideas as to what I've done or not done? [q]jb@Netbook:~/minsoc/sim/run$ ./generate_bench ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v:391: error: Unknown module type: adbg_jsp_module 22 error(s) during elaboration. * These modules were missing: adbg_jsp_module referenced 1 times. * jb@Netbook:~/minsoc/sim/run$[/q] Hi all, trying to run minsoc on a different system to my desktop. I get the following when I run ./generate_bench. Any ideas as to what I've done or not done? jb@Netbook:~/minsoc/sim/run$ ./generate_bench ../../rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v:391: error: Unknown module type: adbg_jsp_module 22 error(s) during elaboration. * These modules were missing: adbg_jsp_module referenced 1 times. * jb@Netbook:~/minsoc/sim/run$

RE: minsoc generate_bench by rfajardo on Sep 17, 2010			rfajardo Posts: 306 Joined: Jun 12, 2008 Last seen: Jan 6, 2020
5. configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v a) comment out line 67, â��`define DBG_JSP_SUPPORTEDâ�� 5. configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v a) comment out line 67, â��`define DBG_JSP_SUPPORTEDâ��

RE: minsoc generate_bench by jb007 on Sep 17, 2010			jb007 Posts: 29 Joined: May 3, 2009 Last seen: Jun 29, 2020
[q]5. configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v a) comment out line 67, Ã¢ï¿½ï¿½`define DBG_JSP_SUPPORTEDÃ¢ï¿½ï¿½[/q] Thanks for that. My mistake for doing it in front of TV late at night. Jim 5. configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v a) comment out line 67, Ã¢ï¿½ï¿½`define DBG_JSP_SUPPORTEDÃ¢ï¿½ï¿½ Thanks for that. My mistake for doing it in front of TV late at night. Jim

RE: minsoc generate_bench by jb007 on Sep 17, 2010			jb007 Posts: 29 Joined: May 3, 2009 Last seen: Jun 29, 2020
[q]5. configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v a) comment out line 67, Ã¢ï¿½ï¿½`define DBG_JSP_SUPPORTEDÃ¢ï¿½ï¿½[/q] Thanks for that. My mistake for doing it in front of TV late at night. Jim 5. configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v a) comment out line 67, Ã¢ï¿½ï¿½`define DBG_JSP_SUPPORTEDÃ¢ï¿½ï¿½ Thanks for that. My mistake for doing it in front of TV late at night. Jim

RE: minsoc generate_bench by mnaveen447 on Feb 10, 2017			mnaveen447 Posts: 1 Joined: Jan 31, 2015 Last seen: Apr 27, 2017
But adbg_defines.v file is not there in min_soc project rar archive.How to get it. But adbg_defines.v file is not there in min_soc project rar archive.How to get it.

RE: minsoc generate_bench by dgisselq on Feb 11, 2017			dgisselq Posts: 247 Joined: Feb 20, 2015 Last seen: Oct 24, 2024
Sadly, much of the OpenRISC team has left OpenCores. You might wish to try your question on the <A href="http://openrisc.io/community">openrisc mailing list</A>, where they tend to be a touch more responsive. <BR>Dan Sadly, much of the OpenRISC team has left OpenCores. You might wish to try your question on the openrisc mailing list, where they tend to be a touch more responsive. Dan

no use

no use

1/1

no use

no use

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.