Quick question : I'm wondering if there's any article or paper about the cycle accuracy of the or1ksim simulator verses the real OpenRISC hardware.

Not to my knowledge, but I imagine it's just like any other comparison between ISS and RTL for cycle accuracy.

A feature of or1ksim is that it can have the number of cycles to perform a task, such as access to peripherals or memory subsystems, specified at runtime via the configuration file.

In my experience or1ksim can be pretty accurate, but as all RTL implementations are a modified harvard architecture (instruction and data ports ultimately share the same bus) I think there's no ability to model any contention on the memory bus, and most memory controllers' access latencies can vary a fair bit depending on use, so you'd probably want a good average access cycle count to plug in. Additionally I don't know if there's any way general bus latency can be modeled, nor burst accesses. I'm also quite certain the floating point instruction execution cycles differ from the RTL implementation, and as I recently added the ability the use a serial multiply unit in the OR1200, the option to indicate this hasn't been added yet.

Functionality has been our main aim of late, rather than accuracy. Perhaps this could be an area where someone could contribute to the project.

But if you tune your memory interface numbers correctly, you could get some pretty accurate numbers, and if your software/algorithm doesn't depend too much on I/O that varies a great deal then I reckon you could get something useful out of it. You can also run a pretty-fast cycle accurate model in ORPSoC, to compare against.

Hi kate

Or1ksim's cycle count is hopeless. It doesn't model the pipeline properly at all. It just adds together one cycle for the instruction and a number of cycles for memory access. The cycles for memory access are based on the data in the config file for the memory, caches and MMUs).

I haven't run tests on OpenRISC, but on a different processor I found you could get huge discrepancy with programs exhibiting pathological behavior which stalls the pipeline frequently (for example strobing the cache).

If you want cycle accurate counts, then use the Verilator model. I have often been tempted to change Or1ksim to just report instruction counts - that would be more honest data.

HTH

Jeremy

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Hi There

Suppose I want to make an multi-core cycle-accurate construction by using or1ksim.
I have 2 questions related to cycle-accurate or1ksim and one question related to multi instantiate to use for multi-core system.
1. If I change the source Verilog code of openRISC to C++ (by Verilator) how can I use generated code specially as library? Is that like Instruction-accurate model and can I follow the instructions which you mentioned in Loosy-Time Model of SoC in TLM2.0?
2. If I want to use your generated cycle-accurate SoC (generated by Verilator) can I use that for instantiate many core? If yes how?
3. I read that or1ksim-0.3.0 has many problems to instantiate many times? Is it same as or1ksim for 0.4.0 and 0.5.0 versions? If I make my or1ksim by verilator still we have such problem or not?

Thanks,
Cheers,

I was very interesting in building a platform contains many instances of or1ksim too. However, the problem is that all variables in or1ksim are implemented as a global variables which makes it impossible to create many instances due to the fact that you need to allocate for each iss instances a specific amount of memory.

I think if you want to get or1ksim running as multicore you need to implement the whole iss from scratch again. I don't know if there are any efforts inside the openrisc community to do that. are there?.

P.S.: Actually there are a work around to create many instances by using inter-process communication technique,but the overhead is huge.

Mainline or1ksim is non-reentrant. I created a patch for 0.3.0 that solves this issue (in a hack). You can find this patch somewhere on the website of or1ksim.

Regards,
Stefan

Hi ag09

It is a big piece of future work. Stefan is the only person to have looked at this, for a version of Or1ksim that is quite a lot older, and I believe just for the CPU. The requirement is captured in bugzilla (http://bugzilla.opencores.org/bugzilla4/show_bug.cgi?id=43).

Stefan's patch is described on the Or1ksim wiki page (http://opencores.org/or1k/Or1ksim#Multiple_instantiations_of_Ork1sim) with full details on Stefan's webste (http://www.wallentowitz.de/or1ksim.html).

HTH

Jeremy

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