1/1 
|
why or32 SPR read has CRC error
by wu__zhi__yong on Jul 19, 2011 |
wu__zhi__yong
Posts: 7 Joined: Jun 24, 2011 Last seen: Jun 24, 2021 |
||
|
I use or1k_soc_on_altera_embedded_dev_kit.tar/gz for or32 based soc debugging,and my hardware platform is ALTERA cycloneIV(EP4CGX150CF23) + usbblaster. I have problem as following, can anyone else help me? (#define debug(...) is enable in file adv_dbg_command.c SRAM_TEST disabled)
[root@localhost adv_jtag_bridge]# adv_jtag_bridge -a 1 -t usbblaster 'usb_blaster' interface using libftdi current latency timer: 2 Enumerating JTAG chain... Devices on JTAG chain: Index Name ID Code IR Length ---------------------------------------------------------------- 0: EP4CGX150CF23 0x028040DD 10 Target device 0, JTAG ID = 0x028040dd IDCODE sanity test passed, chain OK! *** Doing self-test *** select module 1 ctrl wr idx 0 dat 0x1 selreg 0 ctrl rd idx 0 Stall or1k - CPU(s) stalled. Testing CPU0 (or1k) - writing instructions Setting up CPU0 Doing burst write, word size 4, word count 1, start address 0x11 burst op 3 adr 0x11 len 1 Wrote 0x1CRC OK!Doing burst write, word size 4, word count 1, start address 0x3014 burst op 3 adr 0x3014 len 1 Wrote 0x2000CRC OK!Doing burst write, word size 4, word count 1, start address 0x10 burst op 3 adr 0x10 len 1 Wrote 0x0CRC OK!Doing burst write, word size 4, word count 1, start address 0x3010 burst op 3 adr 0x3010 len 1 Wrote 0x400000CRC OK! Starting CPU0! ctrl wr idx 0 dat 0x0 selreg 0 ctrl rd idx 0 ctrl wr idx 0 dat 0x0 selreg 0 ctrl rd idx 0 ctrl wr idx 0 dat 0x0 selreg 0 ctrl rd idx 0 ctrl wr idx 0 dat 0x0 selreg 0 ctrl rd idx 0 ctrl wr idx 0 dat 0x0 selreg 0 ctrl rd idx 0 ctrl wr idx 0 dat 0x0 selreg 0 ctrl rd idx 0 ctrl wr idx 0 dat 0x0 selreg 0 ctrl rd idx 0 ctrl wr idx 0 dat 0x0 selreg 0 ctrl rd idx 0 ctrl wr idx 0 dat 0x0 selreg 0 ctrl rd idx 0 ctrl wr idx 0 dat 0x0 selreg 0 ctrl rd idx 0 ctrl wr idx 0 dat 0x0 selreg 0 ctrl rd idx 0 Doing burst read, word size 4, word count 1, start address 0x10 burst op 7 adr 0x10 len 1 CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry... select module 1 burst op 7 adr 0x10 len 1 CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry... select module 1 burst op 7 adr 0x10 len 1 CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry... select module 1 burst op 7 adr 0x10 len 1 CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry... select module 1 burst op 7 adr 0x10 len 1 CRC ERROR! Computed 0x0, read CRC 0xffffffff Retry... select module 1 burst op 7 adr 0x10 len 1 CRC ERROR! Computed 0x0, read CRC 0xffffffff |
|||
|
RE: why or32 SPR read has CRC error
by jeremybennett on Jul 20, 2011 |
jeremybennett
Posts: 815 Joined: May 29, 2008 Last seen: Jun 13, 2019 |
||
|
Hi wu__zhi__yong I don't know the details of the implementation, but you're going to have to print out the JTAG register received and manually compute the CRC to see which end you believe is correct. Either the hardware is computing the wrong CRC and storing it in the JTAG register or the software is calculating it incorrectly. You'll then know which end to start looking for the problem. HTH Jeremy
-- |
|||
|
RE: why or32 SPR read has CRC error
by wu__zhi__yong on Jul 20, 2011 |
wu__zhi__yong
Posts: 7 Joined: Jun 24, 2011 Last seen: Jun 24, 2021 |
||
|
thank you Jeremy. I'll try it to detect whether hardware problem or software problem.
|
|||
|
RE: why or32 SPR read has CRC error
by nyawn on Jul 22, 2011 |
nyawn
Posts: 173 Joined: Dec 19, 2008 Last seen: May 31, 2023 |
||
|
Hello, I have a guess at the cause of your problem(s).
First, you are using an old version of adv_jtag_bridge - I can tell because you use "usbblaster" on the command line, but the log shows the FT245 driver output. I suggest you upgrade, I've added high-speed support for the FT245 cable. (Use driver 'ft245' on the command line). This will not fix your problem, but it will make the system easier to work with once you do. I'm guessing your real problem is that your bitstream isn't correct, or isn't correctly downloaded to the FPGA. It may be some misconfiguration with the adv_dbg_if defines, or it may be something else. But...you use the '-a' switch on the command line, which no one has ever needed to do before, so I'm guessing that it was doing something else wrong without that. Second, from the logs it looks like you've removed every WishBone access before this particular error occurs (the SRAM test, writing the CPU instructions). Based on your other posts, these were reading back all 1's, which indicates a problem with the JTAG chain. But it's not a cable-level problem, because you read the IDCODE of the FPGA just fine. The error in this log happens the first time you try to read a CPU register, and you get all 1's as the CRC. Double-check your hardware configuration. Then, make sure the adv_jtag_bridge configuration matches the hardware config. If in doubt, grab a recent version of the 'minsoc' project, it has all this already wired up in an easy-to-use example. |
|||
|
RE: why or32 SPR read has CRC error
by wu__zhi__yong on Jul 26, 2011 |
wu__zhi__yong
Posts: 7 Joined: Jun 24, 2011 Last seen: Jun 24, 2021 |
||
|
Ihank you very much.
|
|||
|
RE: why or32 SPR read has CRC error
by wu__zhi__yong on Aug 12, 2011 |
wu__zhi__yong
Posts: 7 Joined: Jun 24, 2011 Last seen: Jun 24, 2021 |
||
|
Finally i found the reason why or32 SPR read had CRC error, i use SignalTap for hardware debugging, SignalTap will also create and use a virtual jtag, so there's two virtual jtag in may design, and ADI's virtual jtag can not works correctly. when i turned off SignalTap function, this problem has been solved.
|
|||
1/1