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about simulation scheme
by czzheng on Aug 22, 2011
czzheng
Posts: 13
Joined: Jul 28, 2011
Last seen: Aug 17, 2025
hi,all
from the docs of openrisc project, i find this project has about 3 different simulation schemes.
1: or1ksim, architecture simulator
2: orpsoc, make rtl-test, it is rtl and software co-simulation
3: orpsoc, make vlt-test, it is verilator generated C model simulation

am i right on this?
if i am wrong, please correct me, if i am right, i have several questions:
1: architecture simulation means that it can mimic the hardware to make program behave as if it is running on hardware. if my code print "hello world", then the or1ksim can show me the string, right?
2: how to use or1ksim. i have installed or1ksim, and i get the user-guide, but i still feel it's far from enough to make me know how to use it.
now, if i wrote a piece of code, how can i use or1ksim to verify that it is right? what the steps.
3: in orpsoc project, i can run: make rtl-test TEST=uart-simple
but i find the printf function is from a seperate file, rather than from a libary. several days ago, i have compiled newlibc, and i can use printf from the newlibc, and even malloc function, but it can not be used in the project here. then my questions is: how to use newlibc in orpsoc enviroment.
4: make rtl-test co-simulation is too slow for a actual program, right? it takes about 2 mins to display "hello" in uart-simple code.
5: make vlt-test c-model simulation, because i have problem running make prepare-vlt, so i have not successfully ran this yet, but i want to ask, how fast it is compared to co-simulation, how to guarantee the generated model is correct, verilator can generate C model from any given RTL?
6. also, how to add my programs into rtl-test or vlt-test enviroment?

thanks to anyone who can give me any information


RE: about simulation scheme
by jeremybennett on Aug 22, 2011
jeremybennett
Posts: 815
Joined: May 29, 2008
Last seen: Jun 13, 2019

hi,all

from the docs of openrisc project, i find this project has about 3 different simulation schemes.

  1. or1ksim, architecture simulator
  2. orpsoc, make rtl-test, it is rtl and software co-simulation
  3. orpsoc, make vlt-test, it is verilator generated C model simulation

am i right on this?

Hi czzheng,

Yes, you are right.

if i am wrong, please correct me, if i am right, i have several questions:

1: architecture simulation means that it can mimic the hardware to make program behave as if it is running on hardware. if my code print "hello world", then the or1ksim can show me the string, right?

This is correct.

2: how to use or1ksim. i have installed or1ksim, and i get the user-guide, but i still feel it's far from enough to make me know how to use it.

now, if i wrote a piece of code, how can i use or1ksim to verify that it is right? what the steps.

or32-elf-gcc myprog.c -o myprog
or32-elf-sim --memory=8M myprog

3: in orpsoc project, i can run: make rtl-test TEST=uart-simple but i find the printf function is from a seperate file, rather than from a libary. several days ago, i have compiled newlibc, and i can use printf from the newlibc, and even malloc function, but it can not be used in the project here. then my questions is: how to use newlibc in orpsoc enviroment.

The tests pre-date newlib being available. Look at the steps taken, and then by hand use the last step, but substitute your program compiled as above.

4: make rtl-test co-simulation is too slow for a actual program, right? it takes about 2 mins to display "hello" in uart-simple code.

This sounds about right. RTL is detailed accuracy, but slow,

5: make vlt-test c-model simulation, because i have problem running make prepare-vlt, so i have not successfully ran this yet, but i want to ask, how fast it is compared to co-simulation, how to guarantee the generated model is correct, verilator can generate C model from any given RTL?

Take a look at Embecosm Application Note 6

. It has some performance measurements - Verilator 130KHz compared with Icarus Verilog 1.4kHz.

6. also, how to add my programs into rtl-test or vlt-test enviroment?

Take a look at an existing program and copy what it does. When you've worked it out, write it up on the Wiki, so others can use it.

HTH,

Jeremy

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Tel: +44 (1590) 610184
Cell: +44 (7970) 676050
SkypeID: jeremybennett
Email:
jeremy.bennett@embecosm.com
Web: www.embecosm.com

thanks to anyone who can give me any information
RE: about simulation scheme
by olof on Aug 22, 2011
olof
Posts: 218
Joined: Feb 10, 2010
Last seen: Dec 17, 2018
hi,all
from the docs of openrisc project, i find this project has about 3 different simulation schemes.
1: or1ksim, architecture simulator
2: orpsoc, make rtl-test, it is rtl and software co-simulation
3: orpsoc, make vlt-test, it is verilator generated C model simulation

am i right on this?

Yes, you are mostly right :)

1: architecture simulation means that it can mimic the hardware to make program behave as if it is running on hardware. if my code print "hello world", then the or1ksim can show me the string, right?

Yes, or1ksim is mostly intended for software developers who can use it test their code without running it on a FPGA board

2: how to use or1ksim. i have installed or1ksim, and i get the user-guide, but i still feel it's far from enough to make me know how to use it.
now, if i wrote a piece of code, how can i use or1ksim to verify that it is right? what the steps.

Start it with o32-elf-sim -f $name_of_configuration_file $name_of_the_elf_binary_that_you_want_to_run

3: in orpsoc project, i can run: make rtl-test TEST=uart-simple
but i find the printf function is from a seperate file, rather than from a libary. several days ago, i have compiled newlibc, and i can use printf from the newlibc, and even malloc function, but it can not be used in the project here. then my questions is: how to use newlibc in orpsoc enviroment.

I'm not sure about this one, but I think that there is a few library functions locally in ORPSoC that are only there as support when you run the test programs. As the rtl tests are intended to test the hardware, we don't want to the full libraries for every test. (Not 100% sure about this one)

4: make rtl-test co-simulation is too slow for a actual program, right? it takes about 2 mins to display "hello" in uart-simple code.

Yes, I think someone said it took 8 days of simulation to boot linux with this method :)

5: make vlt-test c-model simulation, because i have problem running make prepare-vlt, so i have not successfully ran this yet, but i want to ask, how fast it is compared to co-simulation, how to guarantee the generated model is correct, verilator can generate C model from any given RTL?

Verilator is a lot faster than running Icarus, and it should be able to generate models of all synthesizable RTL code. I haven't run vlt-tests myself, but I assume it's working quite well
6. also, how to add my programs into rtl-test or vlt-test enviroment?

Not sure here either, but I think you add create a directory with the name of the test under sw/tests and add .c or .s file (also with the same name as the test). Then you probably have to update the makefile in sim/bin to add the test


Hope this helps, and don't hesitate to ask if something is still unclear
RE: about simulation scheme
by czzheng on Aug 23, 2011
czzheng
Posts: 13
Joined: Jul 28, 2011
Last seen: Aug 17, 2025
thank you jeremybennett and olof :)
i can run or32-elf-sim now as you told me, it feels so good when see myprog give me a nice "Hello world!" :)
and i also tried the debug function, it can work well on my hello world program.

then i come to several new questions�
1� i find that in gdb6.8 directory, there is a user guide about how to use or1k specific gdb,(or1k.pdf after make pdf), but gdb7.2 no longer has that file. maybe it is not changed much between these 2 versions, but i think it's better to keep it. further more, i do my debug test according to this file, and i find it is quite useful, except 2 points:
a): "gdb_enabled and server_port" in section debug in sim.cfg file is no longer that name, it has changed to "rsp_enabled and rsp_port"
b):the "hello world"example in the file can not be compiled successfuly if directly copy those code into a file, but reporting "NOP_EXIT NOP_PUTC" undefined, so there must be some other file missing. so maybe it's better to complete this example or replace it.

2: or32-elf-gdb must be used together with or1ksim? and also must first start a RSP? it can not be used standalone� right?

3: when debug, firstly must modify sim.cfg to enable debug section, but if i do not use debug, then is this sim.cfg needed? in my hello world program, i donnot even specify the uart port, i just use printf funciton, then, do i need to keep section uart in sim.cfg? or each section in the cfg file corresponds to actual hardware module, if no hardware then it can be omitted, right�

4�when using or32-elf-sim run elf or vmem files generated when make rtl-test in orpsoc project, i find it always halt there, no output for a long time.
after ctrl+c, it show a promt like this: (sim),means it also goes to interactive mode, but why executive file generated by orpsoc can not be run by or32-elf-sim. orpsoc make rtl-test can also give expected result, what the method it used? not or1ksim?

5�or32-elf-sim interactive mode, it can set break, can run 1 or N instructions, but i can not find a "continue" which run until it meets a breakpoint. so it may be inconvinent if if must one instruction by one or calculte how many instructions are between 2 break points?
or i have missed something?

thanks

RE: about simulation scheme
by jeremybennett on Aug 23, 2011
jeremybennett
Posts: 815
Joined: May 29, 2008
Last seen: Jun 13, 2019

thank you jeremybennett and olof :)

i can run or32-elf-sim now as you told me, it feels so good when see myprog give me a nice "Hello world!" :)

and i also tried the debug function, it can work well on my hello world program.

then i come to several new questions.

1: i find that in gdb6.8 directory, there is a user guide about how to use or1k specific gdb,(or1k.pdf after make pdf), but gdb7.2 no longer has that file. maybe it is not changed much between these 2 versions, but i think it's better to keep it. further more, i do my debug test according to this file, and i find it is quite useful, except 2 points:

Hi czzheng,

It is rolled into the main GDB manual (gdb.pdf), which should have a target specific section for OpenRISC 1000.

a): "gdb_enabled and server_port" in section debug in sim.cfg file is no longer that name, it has changed to "rsp_enabled and rsp_port"

gdb_enabled and server_port were parameters that controlled the obsolete OpenRISC JTAG protocol. This was deprecated in Or1ksim 0.4.0 and removed in Or1ksim 0.5.0. rsp_enabled and rsp_port are the corresponding parameters for Remote Serial Protocol connections to targets (the GDB standard).

b):the "hello world"example in the file can not be compiled successfuly if directly copy those code into a file, but reporting "NOP_EXIT NOP_PUTC" undefined, so there must be some other file missing. so maybe it's better to complete this example or replace it.

Which "hello world" example is this? Could you give the complete directory and file name.

2: or32-elf-gdb must be used together with or1ksim? and also must first start a RSP? it can not be used standalone right?

That is correct. Or1ksim is also incorporated within GDB as the built-in simulator (that is why you must build and install Or1skim before you build the GNU tools), so you can use it directly as "target sim" in GDB.

3: when debug, firstly must modify sim.cfg to enable debug section, but if i do not use debug, then is this sim.cfg needed? in my hello world program, i donnot even specify the uart port, i just use printf funciton, then, do i need to keep section uart in sim.cfg? or each section in the cfg file corresponds to actual hardware module, if no hardware then it can be omitted, right.

The configuration file gives you detailed control of the Or1ksim simulation. For simple use (as in my previous example), it is sufficient to just specify the amount of memory (which will start at address 0x00000000) using --memory. You can also set up to run with Remote Serial Protocol (RSP) debugging without a configuration file by using:

    or32-elf-sim --memory=8M --srv=51000
    

which will enable debugging via RSP at port 51000.

4: when using or32-elf-sim run elf or vmem files generated when make rtl-test in orpsoc project, i find it always halt there, no output for a long time. after ctrl+c, it show a promt like this: (sim),means it also goes to interactive mode, but why executive file generated by orpsoc can not be run by or32-elf-sim. orpsoc make rtl-test can also give expected result, what the method it used? not or1ksim?

"make rtl-test" runs programs on an Icarus Verilog simulation of the RTL, not Or1ksim. The vmem files are a binary memory image, which are created from the ELF binaries generated by the GNU tool chain. You will need an Or1ksim configuration which matches that of the RTL, and you will need to supply the ELF binaries, not the vmem. If you look at the "make rtl-test" output you should see where the elf files are converted to vmem files.

5: or32-elf-sim interactive mode, it can set break, can run 1 or N instructions, but i can not find a "continue" which run until it meets a breakpoint. so it may be inconvinent if if must one instruction by one or calculte how many instructions are between 2 break points? or i have missed something?

The Or1ksim interactive mode is very simple. For this sort of work, use GDB.

HTH

Jeremy

RE: about simulation scheme
by czzheng on Aug 25, 2011
czzheng
Posts: 13
Joined: Jul 28, 2011
Last seen: Aug 17, 2025
thank you,jeremybennett
the "hello world" program i said is in the or1k.pdf file which is generated after make pdf. for my case, i compiled source code in a directory bld_gdb68, then make pdf, then in ./gdb/doc there is or1k.pdf

in orpsoc project, i can generate elf files too, using make uart-simple.elf for example. but this elf file can not be run by or1ksim.
could it be because of the different libraries used? e.g, printf function.

RE: about simulation scheme
by jeremybennett on Aug 25, 2011
jeremybennett
Posts: 815
Joined: May 29, 2008
Last seen: Jun 13, 2019

thank you,jeremybennett

the "hello world" program i said is in the or1k.pdf file which is generated after make pdf. for my case, i compiled source code in a directory bld_gdb68, then make pdf, then in ./gdb/doc there is or1k.pdf

Hi czzheng,

I don't have easy access to this any more. Could you post a listing here. Then I can see why it won't compile.

in orpsoc project, i can generate elf files too, using make uart-simple.elf for example. but this elf file can not be run by or1ksim. could it be because of the different libraries used? e.g, printf function.

Very likely. Or it is trying to do something not available in your Or1ksim model. For example uart-simple.elf is probably running tests on UART registers - do you have the UART configured appropriately?

What is the error message you get from Or1ksim when you try to run uart-simple.elf. If the program just hangs, it is almost certainly a problem with how it is trying to drive the UART.

HTH

Jeremy

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