I am trying to write a small test program that uses a simple (virtual = physical) version of virtual memory. I turn on the I-MMU and take my first I-TLB miss. I add the mapping in both the match and translate registers for the I-MMU. Upon returning back to the program, I get the same exact I-TLB miss. This may happen dozens of times before the program makes any forward progress. What am I missing?

Is it waiting for the cache miss to actually be satisfied, i.e. a (potentially very slow) fetch from memory?

If it is waiting for the word from memory (it will be a while since I turned the caches off as a precaution), the pipeline should be stalled, and no new TLB misses generated. Note that I get the same exact behavior when I use or1ksim, which tells me that I am doing something wrong.

Problem solved.

After looking at the orlksim code and reading the OR1200 manual a little closer, I realized the TLBs were direct-mapped not fully associative. After updating my itlb miss function to use the N least significant bits of the virtual page number as the set number, everything worked as expected.

I was getting repeated TLB misses until I updated the correct set, so that explains that as well.